CS152 Computer Architecture and Engineering

Homework #3

Spring 2002, Prof Bob Brodersen

Please include the TIME or TA NAME of the DISCUSSION section that you attend as well as your NAME and STUDENT ID. Homeworks and labs will be handed back in discussion sections.

Homework #3: Due Thursday February 21, 2002 in class

1. Consider the circuit below with the NAND gate characteristics listed. (Assume wires have the same capacitance as the input capacitance off all the gates attached to it.)

ILA = ILB = 55 fF
TPAOlh = 0.3 ns
TPAOhl = 0.2 ns
TPAOlhf = 0.0015 ns/fF
TPAOhlf = 0.0012 ns/fF
TPBOlh = 0.2 ns
TPBOhl = 0.4 ns
TPBOlhf = 0.0017 ns/fF
TPBOhlf = 0.0019 ns/fF

What function does this circuit implement?
What is the propagation delay from X to Z through Gates 2 and 4 with high-to-low transitions on both gates? (Hint: this should be load dependent)
What is the input capacitance for input X?
What is the critical path for this circuit?
What is the worst-case propagation delay?

2. Consider if we placed the above logic block between two registers, as pictured below. The registers have the characteristics as listed.

Internal Delay = 0.3 ns
Load dependent delay = 0.0015 ns/fF
Input capacitance = 30 fF
Hold time = 0.5 ns
Setup time = 1.0 ns

What is the clock-to-Q time for register one?
What is the most clock skew we can tolerate if the clock edge arrives at register two before register one?
What is the shortest cycle time we can have for this circuit?

3. Design a finite state machine for an elevator. The elevator travels between two floors. You have the following inputs and outputs:

Inputs:

button1, button2 – asserted when either the button inside or outside the elevator is pressed, stays high until respective acknowledge signal is asserted (ack1, ack2)
floor1, floor2 – asserted when the elevator is at the respective floor

Ouputs:

open – when asserted the doors are opened and kept open, when de-asserted the doors are closed and kept closed
up, down – move the elevator up or down, elevator stops when both are de-asserted, both up and down should never be asserted together
ack1, ack2 – acknowledge that the request for a floor has been served, results in button1 or button2 being de-asserted

4. Consider adding another floor to the elevator in problem 3. In addition to button3, floor3, and ack3 the system now has a 5 second timer so you can know how long to keep the doors open on a particular floor. The timer has the following input and output:

start – an input to start the timer
expired – an output indicating that the 5 seconds has elapsed

Design the FSM for this system.