Selected Papers 

Other Papers on Lecture Page

Communications Systems

1. B. Sklar, "Defining, designing, and evaluating digital communication systems," IEEE Communications Magazine,
vol.31, no.11, pp.91-101, Nov. 1993.

2. R. Prasad, T. Ojanpera, "An overview of CDMA Evolution toward wideband CDMA," IEEE Communications Surveys, http://www.comsoc.org/pubs/surveys, Fourth Quarter 1998, vol. 1, no. 1, pp. 2-29.

DSP Arithmetic

3. P.M. Kogge, H.S. Stone, "A parallel algorithm for the efficient solution of a general class of recurrence equations," IEEE Transactions on Computers, vol. C-22, no. 8, pp. 786-793, August 1973.

4. A. Avizienis, "Signed-digit number representations for fast parallel arithmetic," IRE Transactions on Computers, September 1961.

FIR Implementations 

5. R. Jain, P.T. Yang, T. Yoshino, "FIRGEN: a computer-aided design system for high performance FIR filter
integrated circuits," IEEE Transactions on Signal Processing, vol.39, no.7, pp.1655-1668, July 1991.

6. R.A. Hawley, B.C. Wong, T.-J. Lin, J. Laskowski, H. Samueli, "Design techniques for silicon compiler implementations of high-speed FIR digital filters," IEEE Journal of Solid-State Circuits, vol.31, no.5, pp.656-667, May 1996.

7. C.S.H. Wong, J.C. Rudell, G.T. Uehara, P.R. Gray, "A 50 MHz eight-tap adaptive equalizer for partial-response channels," IEEE Journal of Solid-State Circuits, vol.30, no.3, pp.228-234, March 1995.

8. L.E. Thon, P. Sutardja, F.-S. Lai, G. Coleman, "A 240 MHz 8-tap programmable FIR filter for disk-drive read channels," 1995 IEEE International Solid-State Circuits Conference. Digest of Technical Papers ISSCC '95, pp.82-3, 343, San Francisco, CA, USA, 15-17 Feb. 1995. 

9. D. Moloney, J. O'Brien, E. O'Rourke, F. Brianti, "Low-power 200-Msps, area-efficient, five-tap programmable FIR filter," IEEE Journal of Solid-State Circuits, vol.33, no.7, pp.1134-1138, July 1998.

10. R. B. Staszewski, K. Muhammad, P. Balsara, "A 550-MSample/s 8-Tap FIR Digital Filter for Magnetic Recording Read Channels," IEEE Journal of Solid-State Circuits, vol. 35, no. 8, pp. 1205-1210, August 2000.

11. K. Azadet, C.J. Nicole, "Low-power equalizer architectures for high speed modems," IEEE Communications
Magazine, vol.36, no.10, p.118-126, Oct. 1998. 

Viterbi Decoders

12. P.J. Black, T.H. Meng, "A 140-Mb/s, 32-state, radix-4 Viterbi decoder," IEEE Journal of Solid-State Circuits, vol.27, no.12, pp.1877-1885, Dec. 1992.

13. P.J. Black, T.H.-Y. Meng, "A 1-Gb/s, four-state, sliding block Viterbi decoder," IEEE Journal of Solid-State Circuits, vol.32, no.6, pp.797-805, June 1997.

14. G. Fettweis, H. Meyr, "Parallel Viterbi algorithm implementation: breaking the ACS-bottleneck," IEEE Transactions on Communications, vol.37, no.8, p.785-90, Aug. 1989.

15. G. Fettweis, H. Meyr, "High-rate Viterbi processor: a systolic array solution," IEEE Journal on Selected Areas in Communications, vol.8, no.8, pp.1520-34, Oct. 1990.

16. G. Fettweis, H. Meyr, "High-speed parallel Viterbi decoding: algorithm and VLSI-architecture," IEEE Communications Magazine, vol.29, no.5, pp. 46-55, May 1991.

17. A.K. Yeung, J.M. Rabaey, "A 210 Mb/s radix-4 bit-level pipelined Viterbi decoder," 1995 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, ISSCC '95, pp.88-9, 344, San Francisco, CA, 15-17 Feb. 1995. 

18. G. Fettweis, R. Karabed, P.H. Siegel, H.K. Thapar, "Reduced-complexity Viterbi detector architectures for partial response signalling," Proceedings of GLOBECOM '95, Singapore, vol.1, pp.559-563, 13-17 Nov. 1995.

19. T. Conway, "Implementation of high speed Viterbi detectors," Electronics Letters, vol.35, no.24, pp.2089-2090, 25. Nov. 1999.

20. C.B. Shung, P.H. Siegel, G. Ungerboeck, H.K. Thapar, "VLSI architectures for metric normalization in the Viterbi algorithm," IEEE International Conference on Communications ICC '90, Atlanta, GA, pp.1723-1728, vol. 4, 16-19 April 1990.

21. A.P. Hekstra, "An alternative to metric rescaling in Viterbi decoders," IEEE Transactions on Communications, vol.37, no.11,  p.1220-1222, Nov. 1989.