EE290C: High-Speed Electrical InterfacesSpring 2004 |
| Paper | Date | Day | Presenter | Paper No. | Title | Authors |
|---|---|---|---|---|---|---|
| 1 | Feb. 24 | Tues | Zheng Guo | 13.6 |
8Gb/s Capacitive-Coupled Receiver with High Common-Mode Rejection for Un-Coded Data |
X. Maillard, M. Kuijk Vrije Universiteit, Brussels, Belgium |
| 2 | Feb. 24 | Tues | Zhengya Zhang | 13.7 |
A 2Gb/s 2-tap DFE Receiver for Multi-Drop Single-Ended Signaling Systems with Reduced Noise |
S. Bae, H. Chi, Y. Sohn, H. Park Pohang University of Science and Technology, Pohang, Korea |
| 3 | Feb. 24 | Tues | Pavel Monat | 13.8 |
An 8Gb/s Source-Synchronous I/O Link with Adaptive Receiver Equalization, Offset Cancellation, and Clock Deskew |
J. Jaussi1, G. Balamurugan2, D. Johnson1, B. Casper1, A. Martin1, J. Kennedy1, R. Mooney1, N. Shanbhag1 1Intel, Hillsboro, OR 2University of Illinois, Urbana, IL |
| 4 | Feb. 24 | Tues | Pierre-Yves Droz | 13.9 | A 4Gb/s/pin 4-Level Simultaneous Bi Directional IO Using a 500MHz Clock for High-Speed Memory | J-H. Kim1,
S-A. Kim1, W-S. Kim1, J-H. Choi1, C. Kim1
, S-I. Cho1, S. Kim2
1Samsung Electronics, Hwasung, Korea 2Korea University, Seoul, Korea |
| 5 | Feb. 24 | Tues | Jing Yang | 9.3 |
A Fully Integrated 0.13 µm CMOS 10Gb Ethernet Transceiver with XAUI Interface |
H-R. Lee1, M-S. Hwang1, B-J. Lee1, Y-D. Kim1, D. Oh1 , J. Kim1, D-K. Jeong1, W. Kim1, S-H. Lee21Seoul National University, Seoul, Korea 2Silicon Image, Sunnyvale, CA |
|
6 |
Feb. 24 | Tues | Qingguo Liu | 9.4 |
A 10Gb/s SONET-Compliant CMOS Transceiver with Low Cross-Talk and Intrinsic Jitter |
H.Werker1, S. Mechnig1, C. Holuigue1, C. Ebner1 , E. Romani1, F. Roger1, G. Mitteregger1, T. Blon1, M. Moyal1, M. Vena1, A. Melodia1, J. Fisher1, G. Le Grande de Mercey2, H. Geib11Xignal Technologies, Unterhaching, Germany 2Universität der Bundeswehr, Munich, Germany |
| 7 | Feb. 24 | Tues | Brian Leibowitz | 9.6 |
A Quad-Channel 3.125Gb/s/ch Serial-Link Transceiver with Mixed-Mode Adaptive Equalizer in 0.18µm CMOS |
J.Yang1 , J. Kim2, S. Byun1, C. Conroy1, B. Kim1 1Berkana Wireless, Campbell, CA 2KAIST, Daejon, Korea |
| 8 | Feb. 26 | Thurs | Jianhui Zhang | 19.3 |
A 160-2550MHz Active Clock Deskewing PLL Using Analog-Phase Interpolation |
A. Maxim Maxim Integrated Products, Austin, TX |
| 9 | Feb. 26 | Thurs | Bill Tsang | 19.5 |
On-Chip Jitter-Spectrum Analyzer for High-Speed Digital Designs |
M. Takamiya1, H. Inohara2, M. Mizuno1 1NEC, Sagamihara, Japan 2NEC, Fuchu, Japan |
| 10 | Feb. 26 | Thurs | Sean Kao | 19.6 | Design and Analysis of a Jitter-Tolerant Digital DLL-Based Fraction-of-Clock Delay Line |
J. Burnham1, G.Yeh2 , E. Sun2, C.Yang3 1IRF Semiconductor USA, Cupertino, CA 2Zoran, Sunnyvale, CA 3University of California, Los Angeles, CA |
| 11 | Feb. 26 | Thurs | David Fang | 22.1 |
A 0.13 mm CMOS Four-Channel ADSL2+ Analog Front-Endfor CO Applications with 75mW per Channel |
P. Pessl, J. Hohl, R. Gaggl, A. Marak, G. Glanzer, J. Hauptmann, A. Kahl, S.WalterInfineon, Villach, Austria |
| 12 | Feb. 26 | Thurs | Gang Liu | 22.3 |
A 3V CMOS Quad-Spectrum ADSL CPE Analog Front-End with 5V Integrated Line Driver |
R. Hogervorst1, B. Tourette1, N. Monier1, O. Metayer1 , E. Afifi2, J-C. Delefosse1 , J-Y. Michel11Centillium Communications, Vallauris, France 2Centillium Communications, Fremont, CA |
| 13 | Feb. 26 | Thurs | Ken Oo | 22.6 | A 4Gb/s/pin Dual-Reference Simultaneous Bidirectional I/O Circuit for Memory-Bus Interface |
W-S. Kim1, J-H. Choi2, J-H. Kim2, S-B. Cho2, C-H. Kim2 , S-I. Cho2, S. Kim1 1Korea University, Seoul, Korea 2Samsung Electronics, Hwasung, Korea |
| 14 | Feb. 26 | Thurs | Liang-Teck Pang | 22.7 | A 3.6Gb/s/pin Simultaneous Bidirectional (SBD) I/O Interface for High-Speed DRAM | J. Kim, J. Choi,
S. Shin, C. Kim, H. Kim, W. Kim, C. Kim, S. Cho
Samsung Electronics, Hwasung-City, Korea |