There are some points that need to be clarified (and others that are just
missing. Apologies on my part) for this assignment

1b) The problem states there are two components to the internal loading. The
two components I was referring to were the diffusion and overlap capacitors
so in actuality, there are about 4 different caps you have to worry about
(yes, there is Miller effect but not like in a normal inverter. Think about
where Miller multiplication comes from).

2c) The problem asks you to consider the Miller capacitance. Remember that
this is a special case where this inverter you've made is UNLOADED and we're
asking you to find the Cin to this inverter. Only in this particular case
does looking into an inverter give you Miller cap; in most other cases, you
only have to consider 1x Cgd rather than two. But for this homework,
consider Miller!
(corollary: always remember the input cap of an inverter depends on what its
load is!!)

3) This is just blatant mistake on my part. The values for Vgs you should
use are 0, .5, 1, 1.5, 2, 2.5 (negative values for the pmos). There are
actually 6 graphs per device, the 0 and .5 graphs lay pretty much on top of
each other since the current is near 0 for those gate values. These are
normal pmos and nmos devices so the vds values for the PMOS should actually
be negative as well as the current. They were just displayed this way so it
would be easier for you to just lay one on top of the other and find those
intersecting points.

One last thing, for #1, you defintiely have to consider body effect.

Hope this clarifies any problems that you guys are having on this
assignment!

Henry