Fall 2004

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This semester we will be designing a memory array that consists of 64 32-bit words.

Phase 1 of the project is due November 2 by 5pm.  Project is done in teams of two.  Teams must sign up during the labs on October 26-28. Report template.

Static noise margin paper  pdf

Phase 2 of the project is due Wednesday, November 10 by 5pm. Report template.

Decoder paper  pdf

Phase 3 of the project is due Wednesday, November 24 by 5pm. Report template. (page 2 title is corrected)

Tips for LVS (and DRC) in Cadence

Phase 4 of the project is due Thursday, December 2 by 9am. Report template. Poster tips: Use 9 slides (max 12), put the title and your names clearly on top; clearly show design specifications; outline your approach; specifically show the memory cell, column design, decoder design and layout, interesting simulations; summarize the results; show what would you do differently if you were to start the project all over again).

Follow the instructions to create your poster.  (files you need: ee141_yourname.ppt  and  poster_template.ppt)