Homework Set #2 Solutions

The key to this problem is to understand this picture above. Since we can’t use any equations, it is very convenient to superimpose the load lines on top of each other as illustrated above. Look carefully at the X-axis. Since the voltage across the non-linear load is vout, in order to fit it onto a –(Vdd-Vout), we need to flip it upside down to keep the graph valid.

wpe2.jpg (49765 bytes)

We can simply look at the intersecting points to derive the VTC as shown below:

wpe3.jpg (13145 bytes)

a) With this VTC, we can tell by inspection that VOH=2.3V, VOL=0V, and Vm=1.4. This makes sense since the non-linear load acts simply like a resistor, it will always be sucking down current while the PMOS is trying to raise the load from low to high. Thus we know that VOH can never truly reach VDD=3.3V. It also makes sense that VOL=0V, since the PMOS is turned off when the input is high, we simply have the resistor on the bottom discharging it down to zero.

b) By inspection, we can see that VIH=2V  VIL=1V (note that these answers are approx)

c) To determine a first order approximation of tpHL, we look at our good old load lines and see that for the non-linear load is simply a resistor throughout our input range, and thus we can approximate tpHL as a RC discharge, reaching halfway at about .69RC, where R=23k and C=50fF.  Note that we are assuming that the PMOS is off in this region of operation.  

tpHL=.69*23kW*50fF=.793ns

As for tpLH, we look back up at the load lines and see that assuming we have a step input from Vdd to zero, we will be traveling along the |VGS|=3.3V curve on the PMOS. Be sure to note that the PMOS will initially be pulling 164uA with a 3.3V drop across the drain and source. This gives and equivalent resistance of 3.3V/164uA=20kW. When we reach (VOL+VOH)/2, the PMOS has an equivalent resistance of (3.3-1.15)V/152uA=14.1kW. We can model the PMOS as a resistor with an average of 17kW. The non-linear load operates with a resistance of 2.3V/100uA=23kW. Thus we need to solve the time constant for the circuit below:

wpe2.jpg (5215 bytes)

To solve the time required to charge the output to VOH/2 we can model the circuit as shown below. With the resistor divider there, the highest the output can go is (23/(23+17))*vdd.  This is the value of our approximate VOH. (note that this is not the same VOH we derived in part a). Using this method, we are linearizing a transistor which is inherently non-linear in these large-signal regions.) We can redraw the ckt as so:

Vdd’=23/(23+17)*Vdd   R=17K||23K

wpe6.jpg (3191 bytes)

Thus the final RC time constant to charge the output to vdd'/2 =.69RC=.69*9.7k*50fF=.488ns

  1. To determine the static power dissipation, we simply use P=I*V.

             For Vin=3.3V, the PMOS is turned off, and no current is taken from the supply:

P=0A*3.3V=0mA

For Vin=0V and the ckt is stable, the Vout=Vdd’=(23/(23+17))*Vdd=1.90V. Thus I=1.90/23kOhms=83uA

P=83uA*3.3V=272uW

2)

  1. The final voltage of Vout=Vdd-Vt. Since the source of the NMOS is going to be equal to VOUT, we must use backgate to solve for Vt.

Vout=Vdd-(Vtn+g((|VSB-2f|).5 – (|2f|).5))

Vout=Vdd-(0.6V+.4((|Vout+.6|).5 – (|.6|).5))

By iteration, Vout=2.51V

For the PMOS circuit, it is never turned on, so the final voltage is ideally 0V.

*note: As time goes to infinity, subthreshold leakage will bring the node up to Vdd.

 

b) By raising the bulk above Gnd for the NMOS, we essentially lower the threshold voltage for the NMOS. 

Vtn=VT0+g((|VSB-2f|).5 – (|2f|).5))

  When we raise the bulk, the Vsb term becomes negative(souce=gnd, bulk goes up).  Also note that -2f=+0.6V.  Thus we will get an overall decrease in threshold for the NMOS only.  This increases the current drive of the NMOS but the PMOS is still unaffected.  Since we are only dealing with current drive, the output swing is unchanged.

  Increase Decrease Unchanged Why?

VOH

    

X

No Dependence

VOL

    

X

No Dependence

TpLH

    

X

No Dependence

(Assume step input)

TpHL

  

X

  

Stronger NMOS

Current

VM

  

X

  

Stronger NMOS shifts

Vm to the right.

 

3) The first thing to note in this problem is that the diodes in parallel can be combined into a single ideal diode. Since they act as switches with a "on" voltage of .7V, it doesn’t matter if there’s one, two or 100 in parallel. They are all functionally equivalent. To draw the VTC, there are three scenarios.

wpe7.jpg (6468 bytes)

When Vin=-2.5 D1 is reversed biased and can be taken out. In this region, the current I flowing though the resistors:

I = (2.5-(-2.5V)-.7V)/8k =.54mA à Vout=2.5V-(.54mA)(2k)=1.42V

wpe8.jpg (4719 bytes)

I = (2.5-(-2.5V)-.7V)/8k =.54mA à Vout=2.5V-(.54mA)(2k)=1.42V

When Vin-Vx < .7Và D1 is off

When D1 is on, Vx=Vin-0.7V

When Vin < 1.42V D1 is off, and when Vin>1.42V D1 is on.

When 1.07V<Vin<2.5V à Vout=Vin
When Vin>2.5V, Vx>1.8V, and thus we will not have a 0.7V drop across D2 and Vout stays at Vdd.

Putting this all together, we have the transfer function below

wpe9.jpg (6870 bytes).

b)From the VTC, we see that this functions as a buffer with a limited output swing

c)When Vin=0, the current from the supply =.54mA

Power=(.54mA)(5V)=2.7mW

When Vin=2.5v, there is no voltage drop across R1 and thus

no current drawn from the supply Power=0mW.

However, it was also noted that when Vin=2.5V, Vout=2.5V, and Vx=2.5-.7=1.8V which will be at the verge of the first diode turning on, so we have a discontinuity between 0ma drawn from Vin (which must come from some voltage) and (1.8V-(-2.5V))/(6k)=.71mA
Thus the power would be= (.71mA)(1.8V-(-2.5V))=3mW
At this boundary point, either answer will be acceptable

 

  1. For this problem, when we are comparing hand calculation to SPICE, please note that the two primary sources of discrepancy are that the values of kp=30uA/V^2 and   kn=60uA/V^2 were taken from a 1.2um process and that lambda = 0.  When I wrote up the problem set, I didn't have the spice models yet to determine empirically closer values.   Thus the variance up to 50% in current drive is due to both lower model values of Vt, and k'.  

           To determine Tplh, we want to find the time it takes for the transistor current to charge the output capacitor to Vdd/2. We know from EE40 that I=C(DV/Dt). For the propagation delay, DV=vdd/2, C=150fF, I=average current from the transistors. Thus, Dt=C(DV/I)

wpe2.jpg (32573 bytes)

One thing to note about these new I-V models is that they are essentially made up of two components, a parabola and a straight line. The whole business with this Vmin stuff is to know when to choose which curve. When we cross the boundary of Min(VDSAT, VGS-VT, or VDS), we need to choose between the two curves. In the figure above, we want to follow the blue curve until it intersects with the pink line, then we want to follow the pink line.

             Keeping this in mind, this problem is not too bad.

  1. Since l=0, the average current is equal to the saturation current of the transistors without having to worry about varying values of Vds.

Itplh=Ipmos=kp(W/L)((Vgs-Vt)Vmin-Vmin2/2)

=Itplh=Ipmos=kp(3/1)((2.5-0.6)1.9-1.92/2)=162uA

Itphl=Inmos=kn(W/L)((Vgs-Vt)Vmin-Vmin2/2)

=Itphl=Inmos=kn(1/1)((2.5-0.6)1.9-1.92/2)=108uA

Dt =C(DV/I)

tplh=150fF*1.25V/162uA=1.15ns

tphl=150fF*1.25V/108uA=1.73ns

The Spice Plot is shown below

 

From HSPICE , we have tplh as 1.2ns, and tphl as 1.3ns. These values are more symmetrical then out hand calculations. This variance can be attributed to a larger disparity in the kp and kn ratio to account for a more symmetric result, however, this agreement is quite good for a hand calculation.

b) The plots of the I-V characteristics by hand are given in the load lines below. Generating the load lines is a relatively straightforward process of plugging in values into the current equations and knowing when to use the correct curve.  In comparison to spice, the current drives for  both the pmos and nmos are almost 45% larger different. 

 wpe3.jpg (17697 bytes)

wpe8.jpg (77272 bytes)

NMOS is Given Above:
Note that Vgs increases in steps of .5V

wpe9.jpg (66824 bytes)

 

PMOS is Given Above:
Note that |Vgs| increases in steps of .5V

 

wpe7.jpg (13122 bytes)
Using my hand drawn load lines, this is an approx. VTC. 

wpe5.jpg (66232 bytes)

 

 

If you guys are interested, here is the code for my SPICE decks.

This is for the VTC:

vdd vdd 0 2.5
vin vin 0 pulse(0 2.5 0 250p .25n 20n 40n)

M1 vdd vin vout vdd pmos w=.75u l=.25u
M2 vout vin 0 0 nmos w=.25u l=.25u
cload vout 0 150f
.lib '~ee141/MODELS/g25.mod' TT
.option post=2
.dc vin 0 2.5 .1
.tran .1n 100n
.end

This is for the PMOS:

vdd vdd 0 2.5
vds vds 0 0
vin vin 0 0

M1 vds vin vdd vds pmos w=.75u l=.25u
.lib '~ee141/MODELS/g25.mod' TT
.option post=2
.dc vds 0 2.5 .1 vin 0 2.5 .5
.end

This is for the NMOS:

vdd vdd 0 2.5
vds vds 0 0
vin vin 0 0

M1 vds vin 0 0 nmos w=.25u l=.25u
.lib '~ee141/MODELS/g25.mod' TT
.option post=2
.dc vds 0 2.5 .01 vin 0 2.5 .5
.end