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Introduction to digital integrated circuits. CMOS devices and manufaturing technology. CMOS inverters and gates. Propagation delay, noise margins, and power dissipation. Regenerative logic circuits. Arithmetic, interconnect, and memories. Programmable logic arrays. Design methodologies.
The course will start with a detailed description and analysis of the core digital
design block, the inverter. Implementations in CMOS will be discussed. Next the design of
more complex combinational gates, such as NAND, NOR and EXORs, will be discussed, looking
at optimizing the speed, area or power. The learned techniques will be applied on more
evolved designs such as adders and multipliers. The influence of interconnect parasitics
on circuit performance and approaches to cope with them are treated next. Substantial
attention will then be devoted to sequential circuits, clocking approaches and memories.
The course will be concluded with an examination of design methodologies. CAD Tools (SPICE
and MAGIC) will be used for homeworks, labs and projects.
Will be posted on the web on Tuesdays and are generally due the next Wednesday at
5:00pm in 558 Cory
(in the box placed in front of the desk of Carol Sitea).
Homework Information
M 4-5pm 405
Davis (TBD)
W 4-5pm 285
Cory (TBD)
Th 1-2pm 293
Cory (TBD) - Will by all probability
be canceled!
Discussion Information
M 8-11am , Tu 3-6pm, We 11-2pm, Tu 3-6pm, Fr 11-2pm (TBD)
Laboratory Information
Text: "Digital Integrated Circuits: A Design
Perspective", By Jan Rabaey. The
book is available at ASUC.
Laboratory Manuals: Available on the web-page; handouts provided when necessary.
Midterm #1: Th September 23, 6:30-8pm, 277 Cory, 5th Week (material of lectures 1-8).
EE141:
Digital Integrated Circuits