University of California Berkeley

EE 141 Spring 2008

Laboratory Exercise 2

Introduction to Layout Editing using Cadence Virtuoso

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The objective of this introductory laboratory exercise is to walk you through the process of laying out a CMOS inverter using Cadence’s Virtuoso mask layout editing tool. 

 

At the end of this laboratory exercise, you should be able to:

· Create a layout cell view

· Understand the use of the Layer Select Window (LSW)

· Instantiate MOS transistor cells from the ‘gpdk090’ library

· Wire up the devices using the appropriate layers and vias/contacts

· Use the ruler command to measure distances

· Create/edit layer polygons and wires

· Run the Design Rule Checker (DRC) and verify that your layout has no design rule errors

 

Deliverables for this laboratory exercise: Due at the end of the laboratory session.

· Printout of the completed CMOS inverter layout

· Printout of the DRC report file

 

I. Creating the CMOS Inverter Layout

 

Start up the Cadence IC Front-to-Back (icfb2) tool just as you did to complete Homework 1. You will create a layout view of the CMOS inverter you made for Homework 1.  In the Library Manager window, select the library and cell name of your inverter, as shown below.

 

Make sure that you already have the schematic and symbol views of your inverter.

 

Then using the menu bar, select File → New → Cell View…. This will bring up the Create New File window: 

 

Check the library name, cell name and view name so that you are sure that you are creating a layout for your intended cell.

 

Select ‘Virtuoso’ from the tool pull-down menu and click OK. Two windows will open. The layer-select window (LSW) and the layout editor window.

 

The LSW shows the various layers in this 90nm technology. It is used to select the current active layer (for editing, etc.) as well as controlling which layers are visible/selectable or not.   The layout editor window is where you will edit your designs.

 

A detailed description of the various layers in the LSW can be found in the Design Rules Manual (DRM):

/home/ff/ee141/gpdk090_v3.9/docs/gpdk090_DRM.pdf

 

In the menu bar, select Options → Display…. Make sure that the Display Levels and Grid Controls settings are the same as the ones below. Click OK to dismiss the Display Options window.

 

Make sure that your grid controls, display controls and display levels are as shown.   You can set these as your default settings by clicking the ‘Save To’ button at the bottom of the form.

 

Adding MOS Devices

 

Adding MOS transistors to your layout is similar to adding them in your schematic. To create an instance of the NMOS transistor, use the menu bar and select Create → Instance.... Note that you can also do this using the hotkey ‘i’. The Create Instance window opens. Click on the Browse button to select the layout of the NMOS cell from the design kit library (gpdk090) then click Close.

 

Select the layout view of the nmos1v cell from the gpdk090 library.

 

The Create Instance window should then look like:

 

Again, make sure that you instantiate the correct cell. Also make sure that the length and width of the transistor matches the sizes you have in your schematic.

 

Click on Hide and place the cell anywhere in your layout editor window (using a mouse left-click). Press F3 to unhide the Create Instance window and instantiate a PMOS transistor above the NMOS transistor.

 

Again, make sure that you instantiate the correct cell. Also make sure that the length and width of the transistor matches the sizes you have in your schematic.

 

Press ESC to cancel the Create Instance command. Make sure that the layout editor window is the active (selected) window and then press ‘f’. This command ‘fits’ the current layout into the size of the layout editor window.

 

Note the PMOS transistor on top and the NMOS transistor at the bottom.   You can zoom in and out of your layout by using the hotkeys: · SHIFT-z (zoom out) · CTRL-z (zoom in)   You can pan using the arrow keys.

 

Save your design by using the Design → Save command from the menu bar. To prevent any unexpected loss of data, save your work regularly throughout the course of this laboratory exercise.

 

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UC Berkeley EE 141 Spring 2008

Last modified: 1/31/2008 5:15 PM by Louis Alarcon