University of California Berkeley

EE 141 Spring 2008

Laboratory Exercise 5

Logic Gates

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At the end of this laboratory exercise, you should be able to:

· Create schematics and layouts of NAND and NOR gates using Virtuoso Layout XL.

· Design an XOR gate from NAND gates, NOR gates and inverters.

· Simulate the extracted XOR gate.

 

Deliverables for this laboratory exercise: Due at the end of the laboratory session.

· Printout of the post-layout simulation results for an XOR gate using NAND gates, NOR gates and inverters.

· Printout of the XOR gate schematic and layout.

 

I. Creating the NOR Gate Schematic

 

Create a 2-input CMOS NOR gate as shown below. Create a symbol for this gate and verify its functionality using simulations.

 

Wn = 120nm Wp = 480nm   Note that the labels will automatically be connected to pins with the same names.

 

 

II. Creating the NOR Gate Layout

 

Create a layout view of your NOR gate and click on Tools → Layout XL in the layout editor’s menu bar to enter the Virtuoso  XL editing mode. To transfer the schematic instances and pins, click on Connectivity → Update → Components and Nets from the Virtuoso XL menu bar. The Layout Generation Options window will appear.

 

This is quite a complex form so read the steps carefully.   1. Make sure that the I/O pins, Instances and Boundary boxes are selected. 2. Set the default pin type to Symbolic and the Layer/Master option to Metal1_T. 3. Click Apply. This should update the pin table. 4. Set the Pin Label Shape to Label. 5. Set the Boundary Height to 3.6 microns. 6. Click on the Pin Label Options… to open the Set Pin Label Text Style window (shown below). 7. Make sure the options are the same as the one below, then click OK. 8. In the Layout Generation Options window, click OK.

 

Upon clicking OK in the Layout Generation Options window, the devices and pins in your schematic will be instantiated as shown below.

 

On the top part, you will see the cell boundary. You will place all the components within this boundary.   You will also see the pins, and the transistors. Note that the transistor sizes will reflect the sizes specified in the schematic.

 

Create two 0.6 micron supply rails (one for vdd and one for gnd) similar to the one you made for the inverter. Move the vdd and gnd pins to these rails.

 

Afterwards, create an NWELL rectangle covering the upper half of the cell boundary. Next, add M1_NWELL and M1_PSUB contacts on the appropriate supply rail. Lastly, place all the transistors and pins inside the cell boundary.

 

Your layout should look similar to the one below.

 

 

Notice that while moving the pins or transistors, you will see the interconnect information obtained from the schematic. This will serve as a guide in selecting the best placement of the transistors and pins relative to each other.

 

An interesting function of the Virtuoso XL layout editor is that when two transistors are connected in series, and you place them together, the middle connection will be removed (if no contact is needed there).

 

Place the transistors and pins and use paths to connect them, similar to what you did in previous laboratory exercises. Your layout should look similar to the one below.

 

Remember to check properties of the vdd and gnd pins for the correct Net Expression Property and Default entries.   Note the series PMOS transistors have no contact between them.

 

Run DRC, circuit extraction and LVS on your NOR gate layout and make sure that there are no errors.

 

 

III. Creating the NAND Gate Schematic and Layout

 

Create a 2-input CMOS NAND gate using the same steps as for the NOR gate. You will start with a schematic similar to the one below with W_n = 240nm and W_p = 240nm.

 

Wn = 240nm Wp = 240nm   Note that the labels will automatically be connected to pins with the same names.

 

Again use the same steps you did with the NOR gate to obtain a layout similar to the one below.

 

Remember to check properties of the vdd and gnd pins for the correct Net Expression Property and Default entries.   Note the series NMOS transistors have no contact between them.

 

Again, run DRC, circuit extraction and LVS on the NAND gate and make sure that there are no errors.

 

 

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UC Berkeley EE 141 Spring 2008

Last modified: 3/2/2008 10:59 PM by Louis Alarcon