EE241: Advanced Digital Integrated Circuits

Assignments

Approximately 5 bi-weekly assignments address the material covered in class but not addressed in the design projects. Assignments have to be returned by the assigned time to Lea Barker (558 Cory Hall).
All assignments are posted on this page (no paper copies are provided).

 

 

Problem Sets

 

Models

Modified Models (drain/source area calculation parameter ACM=3 added)

•   0.18 micron CMOS process (TSMC) -Level 49 (BSIM3v3) models
•   0.25 micron CMOS process (TSMC) - Level 49 (BSIM3v3) models
•   0.35 micron CMOS process (TSMC) - Level 49 (BSIM3v3) models

        Original Models

•   0.18 micron CMOS process (TSMC) -Level 49 (BSIM3v3) models
•   0.25 micron CMOS process (TSMC) - Level 49 (BSIM3v3) models
•   0.35 micron CMOS process (TSMC) - Level 49 (BSIM3v3) models

        Other Models

•   0.35 micron CMOS process - Level 49 (BSIM3v3) models
•   Slow
•   Nominal
•   Fast

Manuals

Hspice tips

Available software: http://www-inst.eecs.berkeley.edu/software.html

Hspice manuals: http://www-inst.EECS.Berkeley.EDU/usr/pub/HSPICE.docs/