EE241: Advanced Digital Integrated Circuits

Projects


To foster design innovation and creative thinking, a major part of the class grade is based on a design project. The idea of the project is to study one of the current "hot items" in digital circuit design and to propose, analyze and design a novel solution to one of those problems. The project is performed in groups of two and will span the complete semester.

Schedule

List of 2002 Projects

Joshua Garrett and Al Molnar, "Power Sentient techniques for variable throughput wireless applications"

Benny Warlick, Edward Liao "Very Large SRAMs"

Jonathan Choy and Henry Lam, "Analysis of variable-threshold double-data-rate memory design"

Nathan Chan, Richard Lu, and Danijela Cabric, "Energy-Delay Tradeoff in Low Power, High Speed Digital Processors"

Kenneth Oo and Eddie Ng, "Study of I/O Circuits in Digital Systems"

Kevin Camera, "Low Power Control for Programmable Datapaths"

Shiying Xiong and Jiagen Ding, "The Impact of Parameter Fluctuation on future Circuit Performance "

Jeff Butler, David Chu, "Split-Path Skewed (SPS) CMOS Buffer for High Performance
and Low Power Applications
"

Yuen Hui Chee and Cheongyuen Tsang, "Flip-Flop Reliability Studies"

Qian Yu and Jianjun Dong, "Exploration of Adiabatic Switching Techniques and Charge Restoring for Low-Power Digital Circuits"

Final Presentations

Final presentations are on Thursday May 16, 9am-12pm in Hogan Room, Cory Hall.

Final reports and presentations are due on the web by 8 am May 16.

Midterm Reports

Midterm poster presentations and reports have to be placed on your web pages by 10am on March 21.
Poster presentations are in BWRC on March 21, 11-12:30.

Suggested outline for reports, 4-5 pages long, min font 12:

Posters should have 9-12 slides with title/names/e-mails.  Should state motivation, problem statement, possible solutions from literature, proposed comparison/solution, conditions/assumptions for comparison, analysis outline of proposed design work.