EE241: Advanced Digital Integrated Circuits

Assignments

Approximately 5 bi-weekly assignments address the material covered in class but not addressed in the design projects. Assignments have to be returned by the assigned time in 558 Cory Hall.
All assignments are posted on this page (no paper copies are provided).

 

 

Problem Sets

Homework #1, due February 12 at 5pm in 558 Cory. Solutions.

Simple data post-processing example.  Inv.prl reads the outputs of the inverter simulations, inv.sp and writes out the propagation delay in Results.mat.

Homework #2, due March 9, at 5pm in 558 Cory. Solutions.

Homework #3, due March 30, at 5pm in 558 Cory. Solutions.

Homework #4, due April 8, April 13 at 5pm in 558 Cory. Solutions.

Homework #5, due April 23 at 5pm in 558 Cory. Solutions.

 

Models

Modified Models (drain/source area calculation parameter ACM=3 added)

•   0.18 micron CMOS process (TSMC) -Level 49 (BSIM3v3) models
•   0.25 micron CMOS process (TSMC) - Level 49 (BSIM3v3) models
•   0.35 micron CMOS process (TSMC) - Level 49 (BSIM3v3) models

        Original Models

•   0.18 micron CMOS process (TSMC) -Level 49 (BSIM3v3) models
•   0.25 micron CMOS process (TSMC) - Level 49 (BSIM3v3) models
•   0.35 micron CMOS process (TSMC) - Level 49 (BSIM3v3) models

        Other Models

•   0.35 micron CMOS process - Level 49 (BSIM3v3) models
•   Slow
•   Nominal
•   Fast

Manuals

Hspice tips

Available software: http://www-inst.eecs.berkeley.edu/software.html

Hspice manuals: http://www-inst.EECS.Berkeley.EDU/usr/pub/HSPICE.docs/