EE241:
Advanced Digital Integrated CircuitsEE241:
Advanced Digital Integrated CircuitsA report is expected at both week 9 and week 15. To make the results available to the complete group and to make your results more dynamic, you will be required to provide them as web-entries. For those of you not familiar with the creation of a web-page, please refer to A Beginners Guide to HTML . Excellent web-page composers exist and most word processing and presentation tools provide a web output generator.
Tsutung Chien, "Optimization techniques - yield vs. energy vs. delay tradeoffs"
Chinwuba Ezekwe, "Ultra-low voltage design for interconnections"
Farhana Sheikh, Vidya Varadarajan, "The impact of device-width quantization on digital circuit design using double-gated MOSFET structures"
Wei-Hung Chen, Yuan-Shih Chen, "Compensating the bitline leakage in low-voltage SRAMs"
Anshi Liang, Jason Stauth, "Study of ring-oscillator structures for digital pulse-width and phase modulation applications"
Eric Chung, "A study and comparison of reconfigurable adders"
Zhengya Zhang, Zheng Guo, "Active leakage control with body bias and sleep transistors"
Peter Chan, Mingcui Zhou, "Design of DPLL for data-link in retinal prosthesis" presentation
Dennis Chang, "A study of regularly structured Wallace tree multiplier"
- Ultra-low voltage design for interconnections - error behavior of 50 mV swings on wires
- Ultra-low voltage logic
- Use of self-timing to address leakage
- Analysis in the energy-delay space of regularly-structured datapaths.
- Design of regularly structured tree multipliers.
- Partitioned datapaths for DSP
- Soft error robustness of logic.
- Leakage compensation in bitlines.
- Impact of adaptive body bias and supply voltage scaling on compensating the parameter variations.
