This course will cover the analysis and design of digital integrated circuits. Emphasis will be on CMOS technology, though Bipolar and BICMOS technologies will also be covered. The course will emphasize design through projects, and will require extensive use of MAGIC for circuit layout, and HSPICE (circuit simulator) and IRSIM (switch-level simulator) for simulations. The major areas of emphasis include:
1. 
A Quick Review of Device Physics: Review the basic operation of semiconductor devices and introduce the device models (both static and dynamic) to be used in the rest of the course. Large signal and charge control models for MOS and Bipolar technologies will be developed.
Static analysis of the CMOS inverter: VTC, Noise margins, Fan-in/Fan-out, etc.
Dynamic analysis of the CMOS inverter: Layout and design rules, modelling of parasitic capacitances (junction, gate, interconnect), propagation delay computation (for both short and long channel devices).
Power Consumption and Power Delay Product: Computation of the four components of power consumption - switching, short-circuit, leakage, and static - and analysis of relative importance. Influence of scaling the power supply voltage, threshold voltage, and feature size on the power-delay product. Simulation techniques for power-delay product using SPICE and IRSIM.
Static and Dynamic Analysis of the Bipolar ECL Inverter: Steady state and transient response.
3. Design of Combinational Logic Gates Using Different Circuit Styles:
Static CMOS Design: Conventional complementary CMOS, ratioed logic, pass transistor logic, DCVSL
Dynamic CMOS Design: Basic principles (precharge and evaluation), charge sharing, cascading dynamic gates, DOMINO, NORA, Pass-transistor, Self-timed DCVSL.
Power Consumption in CMOS Gates: Switching activity of a gate (influence of signal statistics, signal correlations, and circuit topologies), glitching in cascaded logic, transistor sizing for low-power, voltage scaling. Analysis using IRSIM and SPICE.
High Performance Logic Design: Differential ECL, Other Bipolar logic styles, BICMOS logic gates
4. Bit-slice Design of Arithmetic Blocks:
Adder Design: Ripple carry, carry bypass, carry-select (linear and square root), logarithmic lookahead, etc. Various circuit styles will be considered (static vs. dynamic, pass-gate vs. conventional CMOS, and synchronous vs. self-timed).
Other arithmetic structures such as multipliers, shifter, etc.
5. Coping with Interconnect and I/O:
Modelling Interconnect: Capacitive parasitics
Drivers for Large Capacitance On-chip and Off-chip Busses: Cascading CMOS inverter stages and optimal transistor sizing for minimum delay, tri-state buffering, level conversion I/O to interface mixed voltage systems, and BICMOS drivers.
Minimizing Power in Driving Large Capacitances: Optimal transistor sizing trading delay and power, low-swing interconnect, and adiabatic charging.
Resistive Parasitics: modeling RC-delays, techniques to reduce RC delays and ohmic drops.
Inductive Parasitics: Voltage drops
6. Design of Sequential Circuits:
Static Sequential Circuits: Bi-stability, Master-slave and Edge-triggered flip-flops, CMOS and Bipolar
Dynamic Sequential Circuits: Two-phase latch, C
MOS latch, True Single Phase Clocking (TSPC).
Schmitt Trigger: Emitter-coupled schmitt trigger, and CMOS schmitt trigger.
Timing Issues in Digital Circuits: Set-up/hold, clock skew, synchronizers, self-timing, clock generation and distribution.
7. Basics of DSP Architectures:
Basic trade-offs: Custom vs. programmable architectures, time-multiplexed vs. parallel architectures, bit-serial vs. bit-parallel, assignment/scheduling, flowgraph transformations (e.g., algebraic transformations, retiming/pipelining, loop transformations), memory architecture, distributed arithmetic, etc.
8. Techniques for Low Power Design:
Voltage Scaling Techniques: area-power trade-offs (pipelining, parallelism, algorithmic transformations), threshold voltage reduction, multiple-threshold devices. High-efficiency DC-DC conversion techniques (zero voltage switching, transistor sizing for low-power, layout strategies for power transistors, etc.).
Switched Capacitance Reduction: operation reduction, optimizing data representation and signal correlations, minimizing spurious transitions, optimizing sequencing of operations, activity driven power down, and optimizing arithmetic structures and circuits.
9. Design of Memory and Array Structures:
Introduction: Memory classification and trends
ROM and PLA: Basic cells, NOR and NAND structures, transient performance, precharged arrays.
SRAM and DRAM: Organization (architecture), cell-design, drivers, sense-amplifier design, ATD.
Jan Rabaey, Digital Integrated Circuits: A Designers Perspective, Prentice Hall, to be published in 1995 (print proofs will be available).
EECS 6.012 (Microelectronic Devices and Circuits)
There will be significant emphasis on the design aspect of the digital design process. This is reflected in the grading strategy for the course. The grade will be based on performance in the weekly homeworks and software labs (using MAGIC), two small design projects (the first on bit-slice adder design and the second on sequential circuits), and two exams. The final grade is calculated using the following weights:
1. Homeworks and software labs 10%
