II. 2114 4K x 1 STATIC RAM
The data sheet for this component is attached. This design dates from the early 1970's, so performance is rather poor by today's standards. However, this is an advantage for us because it means reasonably accurate measurements can be taken with the chip plugged into a superstrip rather than a carefully designed circuit board.
Measure the static DC voltage transfer characteristic from any one address input to the output. Load the output with one standard TTL gate (7400 series) plus a l Kohm resistor to ground. Determine the output levels VOH and VOL and the noise margins NML and NMH. Note that you will have to wire the chip enable input low and the read/write input high. All unused address inputs should be wired low. Unused data pins should be left floating.
III. DYNAMIC MEASUREMENTS
Devise an experiment to measure the address access time (tA), chip enable access time (tCO), read cycle time (tRC), and previous read data valid time with respect to address transistion (tOHA). See data sheet for definition of these times. Output load should be 1 TTL gate plus 100 pF to ground for this part. Make these measurements for VDD = 4.5 V, 5 V, and 5.5 V. Compare your results with the specifications on the data sheet.
If time permits, measure the read access time for several address locations in order to observe the variation of this parameter according to physical location of memory cells on the chip.