The topic of this project is to design one full adder cell in the standard 1.2 
m CMOS technology. It means that you have to realize the following equations.
The primary goal of the project is to minimize the worst case propagation delays of the sum and the carry generation. The secondary objective is to minimize the area. The propagation delay of the sum must be less than 8 nsec. and of the carry less than 2 nsec. The faster and the smaller your circuit, the better your grade.
The design will be graded on the A.t
scale (a measure often used in industry). To take into account the longer delay of the sum, the exact grading will be on A.(4.t
+ t
) . t is the worst case propagation delay of the carry, t the worst case propagation delay of the sum.
The full adder cell has to fulfill the following specfications:
The design style must be fully static CMOS (i.e. no dynamic, pseudo-NMOS). You are allowed to use pass transistor logic internally in the cell only if the outputs are buffered. This means that each output needs to have "driving capability." "
Inputs: To mimic real-life environments, it is assumed that inputs A,B, Cin come from a minimum size invertor. Those minimum size invertors are driven by ideal voltage sources. The ideal voltage sources have rise and fall times of 100ps. The inputs are in ~e141/INFO/proj1.spice.
Outputs: At the output of the full adder cell, an identical full adder cell is connected, as shown in Figure 1. This means that the sum output is used as an A or B input of the next full adder cell. Similarly, the Cout output is used as a Cin of the next cell.
Delays: Optimize for the worst case propagation delay, tp
or tp for both the sum and the carry output. You have to determine which are the worst case propagation delays. Justify in your report. Apply the input combinations of Table 1. Remark that Table 1 does not contain all possible transitions. If your design needs another input transition combination, add it to the input waveforms.
Layout your cell in Magic. Your layout must be free of design rule errors, and must include wells and appropriate contacts to all wells. Each input, output, and power supply wire should be brought to the edge of your cell with poly, m1, or m2 so that someone using your circuit could make all connections with a single wire for each signal. For example, all your Vdd lines should be tied together and brought to the edge of your cell.
A, B enter on the left of your cells, Cin from the bottom. Cout leaves the cell at the top, at the same position, as Cin enters. (This allows to stack cells upon each other.).The Sum leaves at the right of your cell.
The area of your layout will be the area of the smallest rectangle in which your layout fits. In other words, select your top level cell, type `b' (for box) and magic will tell you the dimensions of your cell. Magic will automatically check for almost all design rule violations. However, it won't check for wells that are too small, so you are responsible for making sure that your wells overlap all diffusions by at least 5 lambda; well contacts, by 2 lambda. (This is really quite simple. It is only included in these instructions to make sure that everyone uses the same rules for wells so that we measure area fairly.)
You should verify your design by running spice on the circuit extracted from the Magic layout. Measure the propagation delay for the worst case transition and measure total energy consumed by your circuit with the input waveforms in ~e141/INFO/proj1.inputs. (You will not be graded on energy consumption, but you should include it in your report.)
The quality of your report is as important as the quality of your design. Organization, conciseness, and completeness are of paramount importance. Use the attached cover sheet and fill in the table; be sure to use the correct units. In addition, you should discuss your overall design philosophy and the important design decisions you made. Also include schematics, a flea plot of your magic layout, and a carefully selected subset of pertinent spice inputs and outputs. A good report is like a good layout: it should perform its function (convey information) in the smallest possible area with the least delay (to the reader) possible.
