A video processing chip consists of 16 parallel identical processors, placed in a gridlike fashion, and two memory-banks, as shown in Figure 1. The chip operates at a 3 V supply voltage. Each processor requires a single clock 
and presents a clock load of 5 pF. The two memory banks each have two clock contacts, each of which presents a load of 10 pF. We would like to run the chip at a clock speed of 50 MHz. The clock rise and fall times at the processor connections should be smaller than 0.75 nsec, while the clock skew between any two processors, or processor and memory, should be smaller than 0.15 nsec.
Your task is to be the chief designer of the clock network. You are free to choose the number and the placement of the buffers and drivers, the routing material and wire width, the distribution approach, etc. The reference clock is provided through a reference pin. The clock network should present a maximum load of 50 fF to the incoming clock signal.
Since the clock is one of the dominant power consumers, we would like you to find this approach that minimizes the power consumption of the clock distribution network (including drivers, fanout and interconnect).
At the on-set of the project, you are to choose your clocking strategy. Use first order models to analyze the delays of wiring and to determine your buffering strategy. You are allowed to use any logical style to implement your buffering strategy - e.g. reduced swing clock distribution is an allowable option. YOUR FIRST ORDER MODEL MUST BE PRESENTED IN THE REPORT. Next you are to design the clock network and the drivers, and place them on the chip floorplan in magic. Do not bother with connecting the supply rails. The MAGIC floorplan is provided in ~ee141/PROJECT2/video_proc.mag. Extract the circuit electronics and the parasitics, and verify your model with SPICE. Use the 
-3 model for the long wires. The resistance numbers are given in the reader. Fine-tune your network so that it meets the requirements.
POWER SUPPLY: A power supply of 3V should be used.
PERFORMANCE METRIC: The input clock has a period of 20 nsec and 100 psec rise and fall times.
CLOCK SKEW: The clock skew between any two processors, or between a processor and a memory bank should be smaller than 0.15 nsec.
NOISE MARGIN: The minimum clock swing should be 0.5 V. At the clock connectors of processors and memories, the clock should have a full swing between 0 and 3V.
RISE AND FALL TIMES: The rise and fall times of the clock signals at the clock nodes (10% to 90%) should not exceed 0.75 nsec.
LOAD CAPACITANCE: Each processor present a clock load of 5 pF, while each memory clock connection equals 10 pF.
POWER CONSUMPTION: The consumption should contain the dissipation of the total clock network, including the power to drive alll the capaciatnces, as well the intrinsic consumption of drivers and buffers. It is easy to see that the minimum possible dissipation equals 54 mW.
The quality of your report is as important as the quality of your design. One must sell the design by justifying the design decisions and providing all the vital information, while eliminating the unneccessary materials. Organization, conciseness, and completeness are of paramount importance. Use the attached cover sheet and fill in the table; be sure to use the correct units. In addition, you should discuss your overall design philosophy and the important design decisions you made. Include schematics, a plot of your magic layout, and the resulting SPICE outputs and decks. Prove that your alleged results are TRUE by providing the crucial plots. The total report should not contain more than four pages. You are not allowed to add any other sheets, except SPICE files or important plots. It should be based on the following outlay:
Page 1: Overall strategy + first-order model, Motivation
Page 2: Transistor diagram - annotated with transistor sizes. Comments.
Page 3: Analysis of extracted design demonstrating that the requirements are met.
Page 4: Layout of the design + comments.
