A diagram of the comparator is given Figure 1. The only given factor is the required functionality. It is up to you to determine the logic diagram to implement these functions
The goal of this project is to design a comparator that compares two four-bit numbers A and B and returns two signals: LT (A > B) and EQ (A == B). The comparator has to be implemented in the standard 1.2 
m CMOS technology. The project is to be performed in groups of 2. Preferably, use the same partner as you use in your labs.
A diagram of the comparator is given Figure 1. The only given factor is the required functionality. It is up to you to determine the logic diagram to implement these functions
The goal of the project is to maximize the performance of the comparator. This is quantidied by the worst-case propagation delay of the structure. Since unbridled optimization of the performance could lead to extremely large designs, we put a constraint on the area by attempting to minimize the 
product instead, or the product of the propagation delay and the area of the comparator.
At the on-set of the project, you are to choose one of the following logic families: pseudo-NMOS, DCVSL, CPL, or dynamic (Feel free to suggest any other logic family you might be interested in as long as it is not complimentary CMOS). This decision should be conveyed to me by Friday October 5. A sign-up sheet will be made available in ~ee141/PROJECT1. You cannot come back on that decision after friday. The grading will be made relative to designs in the same family. You may assume that the complements of the inputs are available when you are using a differential logic style.
POWER SUPPLY: A power supply of 5V should be used.
PERFORMANCE METRIC: The propagation delays for static designs is defined as the time interval between the 50% transition point of the inputs and the 50% point of the worst-case output signal. To determine the worst-case propagation delay, use the following input pattern : A = (0000) and B = (0001) with the left-most bit being the msb. This should set both LT and EQ to 0. Make sure to set the initial values such that this pattern causes a transition at both EQ and LT. Note that for dynamic designs, any duty cycle may be used for the clock, but the propagation delay is defined as the distance beteen the 50% pint of the precharge clock, until the worst-case output has reached the 50% point (it does incorparates the sum of precharge and evaluation periods)!
AREA: The area is defined as the smallest rectangular box that can be drawn around the design.
V
, V
, NOISE MARGINS: You are free to choose your logic swing. The noise margins should be at least be 10% of the voltage swing. Test this by computing the VTC between one of the inputs and the output signals (with the other outputs set to the appropriate values) for a static design. For a dynamic circuit, apply an input signal with a 10% value added to the input and observe the outputs.
RISE AND FALL TIMES: All input signals and clocks have rise and fall times of 500 psec. The rise and fall times of the output signals (10% to 90%) should not exceed 1 nsec.
LOAD CAPACITANCE: Each output bit of the comparator should have a 200 fF load.
The comparator should be laid out using Magic.
Your layout must be free of design rule errors, and must include wells and sufficient contacts to all these wells. Each input, output, and power supply wire should be brought to the edge of your cell with poly, M1, or M2 so that someone using your circuit could make all connections with a single wire for each signal. For example, all power lines should be tied together and brought to the edge of your cell. Try to keep your design as regular as possible since a parameterizable and repetitive design is substantially more successful than a "spaghetti" circuit.
Use common sense in laying out your circuit and remember that long transistors must be built properly!
Analyze the circuit by first extracting from the layout, then using SPICE to simulate the design. Prove the functional operation of your circuit using either SPICE or IRSIM.
The quality of your report is as important as the quality of your design. One must sell the design by justifying the design decisions and providing all the vital information, while eliminating the unneccessary materials. Organization, conciseness, and completeness are of paramount importance. Use the attached cover sheet and fill in the table; be sure to use the correct units. In addition, you should discuss your overall design philosophy and the important design decisions you made. Include schematics, a plot of your magic layout, and the resulting SPICE outputs and decks. Prove that your alleged results are TRUE by providing the crucial plots (don't forget to mention the input patterns you used to obtain those plots). The total report should not contain more than four pages. You are not allowed to add any other sheets, except SPICE files or important plots. It should be based on the following outlay:
Page 1: Abstract, Logic Diagram, Remarks and motivations
Page 2: Transistor diagram - annotated with transistor sizes and worst-case timing path. Plot showing the functional operation of the cell. Comments.
Page 3: Timing simulation - derive value of worst-case path - comments on the optimizations.
Page 4: Layout of the design + comments - Show obtained area.
Remember, a good report is like a good layout: it should perform its function (convey information) in the smallest possible area with the least delay (to the reader) possible.
