The topic of this project is to design an 8 bit programmable counter in the standard 1.2 
m CMOS technology. The goal is to maximize the speed, while minimizing the power consumption. Grading is based on the "Energy-delay" product.
The counter should implement the following functions:
When the counter reaches "FF" it returns back to "00".
Speed is measured by the maximum clock frequency which can be applied to the circuit. Energy corresponds to the total energy consumed by one bit slice of the data path for the input patterns specified in table 1.
The design should fulfill the following specfications:
You can start from a common full adder cell, whose layout (in magic format) can be downloaded by clicking here .
You have total freedom in choosing the design style of the registers (static, dynamic) and the clocking strategy (single phase, two phase, two phase non overlapping, etc.)
The 8 bit adder is a ripple adder. It is constructed by stacking 8 full adder cells upon each other.
You are free to select the power supply ! Lowering the power supply will reduce the energy consumption, but will increase the delay.
Inputs: The inputs to the circuit come from ideal voltage sources. Ideal voltage sources have rise and fall times of 1ns. Inputs change 4ns after the falling edge of Vphi (see the file ~e141/INFO/project2/proj2.inputs for an example.) 4ns is measured at the 50% points, as shown on the timing diagrams at the end.
Clock Inputs: Clock inputs come from clock buffers. Depending your clock strategy, you will need one or more clock buffers. Different type of clock buffers are described in the file ~e141/INFO/project2/proj2.inputs. You are allowed to change the W/L of the second invertor to speed up your clock or the rise and fall times. Include the energy of the clock buffers in your total energy. Remember, clock buffers are loaded by 8 bit slices.
Outputs: At the output of the counter, i.e. at each bit of "count", a load of 100fF is connected. The Cout of one bit-slice is the Cin of the next bit-slice. The Cout of the MSB bit slice is not used.
To determine the maximal clock frequency: the inputs to the register should have reached 90% of the final value before the clock edge can fall. See the timing diagrams at the end.
Layout one bit slice in Magic.
Your layout must be free of design rule errors, and must include wells and appropriate contacts to all wells. Each input, output, and power supply wire should be brought to the edge of your cell with poly, m1, or m2 so that someone using your circuit could make all connections with a single wire for each signal. For example, all your Vdd lines should be tied together and brought to the edge of your cell. Inputs enter on the left of your cells, Cin from the bottom. Cout leaves the cell at the top, and the outputs leave at the right of the bit slice. The same layout rules concerning wells and measuring the total area, apply as for the first project.
You should verify your design by running spice on one bit slice on the circuit extracted from the Magic layout. Measure the single worst propagation delay and measure total energy consumed by your circuit for the input sequence of Table 1.
Those Spice simulation should give you enough information to estimate the worst case delay on the critical path for an 8 bit counter.
Extract 8 bitslices for IRSIM and verify your critical path computation with IRSIM.
The quality of your report is as important as the quality of your design. Organization, conciseness, and completeness are of paramount importance. Use the attached cover sheet and fill in the table; be sure to use the correct units. In addition, you should discuss your overall design philosophy and the important design decisions you made. Also include schematics, a flea plot of your magic layout, and a carefully selected subset of pertinent spice inputs and outputs. A good report is like a good layout: it should perform its function (convey information) in the smallest possible area with the least delay (to the reader) possible.
Timing diagrams are shown on the next page.
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