EECS 141: DIGITAL INTEGRATED CIRCUITS - FALL 1989
DESIGN PROJECT 2 : A Dynamic Memory Cell
Due Thursday November 30 before 11:10am.
The task of this project is to design a dynamic memory cell. An overview of the complete memory array is given in Figure 1. One single column contains 64 cells, while a row contains 8 cells. The total memory can thus store 512 bits.
We would like to use the memory in a system, driven by a 10 Mhz clock. The system uses two clocks, $PHI 1$ for precharge and $PHI 2$ for evaluation. The relative duration of each of the clocks is up to you, as long as the period equals 75 Mhz (Figure 2).
The sense amplifier used to detect a signal is a simple CMOS invertor (transistor sizes undetermined). The bitlines are precharged using an NMOS transistor.
The transistor cell to be used is a dynamic 3 transistor cell as shown in Figure 3.
The goal of this project is to design the memory cell so that the speed requirements are met. Furthermore, it is obvious that we want the cell to be as small as possible.
The project report should contain the following information :
A detailed hand analysis of the cell and a clear description of how you decided on the device sizes for the cell, the precharge transistor and the sense inverter.
Layout of the 3 transistor cell using the MOSIS 2u SCMOS process (lambda = 1). Remember that this cell has to fit into an array. Make sure that your cell connects nicely to its neighbour.
Detailed SPICE analysis of the dynamic behavior of your cell (Read and Write). It is clear that a total simulation of the array with SPICE is hopeless. Simplify your simulation model in such a way that only one cell is included, as well as the precharge device and the sense amplifier. Describe in you report how you modeled the effects of the other cells.
You may use the following assumptions in your derivations and simulations :
- The word-lines and the write bitline are driven by voltage sources with ideal steps (i.e. infinite slope).
- Take only the capacitance of the bit- and wordlines into account. IGNORE the resistance. This will give you optimistic results but simplifies the analysis. You should however keep the resistance of the bit- and wordlines into account when you layout your cell. Long wires in polysilicon are definitely not the right way to go. Poly-metal contacts also introduce resistance.
Grading will be based on the following topics:
Area of the cell (40%) (A penalty will be applied if the speed requirement is not met).
Quality of the SPICE simulation. Especially the accuracy of the model will be examined (20%)
Clarity of the report. Description of the design strategy. (40%)
A standard result sheet will be passed around. This should be first page of the final report.
The SPICE model of the 2-micron scmos process is given below :
.model n nmos vto=0.7 tox=490e-10 nsub=4.5e15 xj=0.35e-6 ld=0.31e-6 uo=690 rsh=22 cgso=2.20e-10 cgdo=2.2e-10 cj=90e-6 cjsw=675e-12 mj=0.45 mjsw=0.35 pb=0.60
.model p pmos vto=-0.7 tox=490e-10 nsub=4.3e15 xj=0.10e-6 ld=0.4e-6 uo=340 rsh=86 cgso=2.8e-10 cgdo=2.8e-10 cj=195e-6 cjsw=385e-12 mj=0.51 mjsw=0.36 pb=0.70
Cell Size : The cell size is defined by its bounding box, which is the rectangle defining the cell AS IT WOULD BE REPEATED in the memory array.
Transistor Sizes : M1, M2 and M3 refer to the memory cell transistors as defined in Figure 3 of the project assignemnt.
SPICE Simulations - Consider the following constraints when deriving your SPICE results :
- The Sense Amp should be able to drive a 0.5pF load.
- The Precharge time is defined as the time to precharge the read-bitline from 10% till 90 % of its value. Note however that it is wise to make the duration of $PHI 1$ longer than this time, since too low a precharge value Also note that the initial voltage on the read-bitline is NOT zero volt, but depends on how far you discharge the bitline during the read operation. could reduce the noise margin of your memory.
- The Write time is defined as the time for writing a "1" in the memory (given that the stored value is a "0"). It is measured from the time the write-wordline goes high till the voltage on the storage capacitor reaches 90% of its value.
- The Read time is defined as the time for reading a "1" stored in the memory. It is measured from the moment that the read-wordline goes high till the output of the sense-amp reaches 90% of its final value (for a load of 0.5pF as discussed above).
- The power consumption per 75 Mhz Cycle is for the case a "1" is read from the memory. The computed value should be the power consumed in a SINGLE column and should include the power dissipated in the sense amp. HAND computations are sufficient here.
Do NOT use 45 degree lines - only vertical and horizontal geometries are allowed.
Only ONE metal layer is allowed. Do NOT use metal2.
Wiring capacitance estimations :
Metal1 To Ground (on Field Oxyde) : 0.03 fF/$MU m sup 2$
Polysilicon To Ground (on Field Oxyde) : 0.05 fF/$MU m sup 2$
To speed up the read time, you may use an ASYMMETRICAL sense inverter ($V sub M$ different from 2.5V). However the noise margin at the bit line should be at least 0.5V. You should prove with SPICE that reducing the precharge voltage on the bitline with 0.5 Volt does NOT flip the the sense amp in the other direction.