DESIGN PROJECT 1 : The Buffering Problem

Due Thursday October 19 before 11:10am.

A minimal size inverter, whose layout is given in Figure 1, is the last stage of a complex ALU (Arithmetic and Logic Unit), used in a microprocessor. The output of the ALU has to connect to the computer bus. Unfortunately, due to the large fanout, the bus represents a load capacitance of 5pF. In order to be able to drive that large capacitance fast enough, a driver circuit has to be included as shown in Figure 2. The driver consists of 2 cascaded inverters (Figure 3).
The goal of this project is to design the driver circuit, such that the propagation delay between nodes A and B (Figure 2) is smaller than 6 nsec. Of course, we want to implement this cicrcuit in as small an area as possible for a minimal power consumption !
The project report should contain a detailed layout of the driver using the 2 micron MOSIS scmos process (lambda = 1). Furthermore, the report should contain the values of the total area, propagation delay between nodes A and B and the power consumption of the device. The propagation delay and power consumption should first be estimated using hand calculations (based on the capacitor values as obtained from the actual layout). SPICE simulations, proving the validity of the stated results, should be included. Grading will be based on the quality of the circuit (based on area, speed and power considerations).
The SPICE model of the 2-micron scmos process is given below :

.model n nmos vto=0.7 tox=490e-10 nsub=4.5e15 xj=0.35e-6 ld=0.31e-6 uo=690 rsh=22 cgso=2.20e-10 cgdo=2.2e-10 cj=90e-6 cjsw=675e-12 mj=0.45 mjsw=0.35 pb=0.60

.model p pmos vto=-0.7 tox=490e-10 nsub=4.3e15 xj=0.10e-6 ld=0.4e-6 uo=340 rsh=86 cgso=2.8e-10 cgdo=2.8e-10 cj=195e-6 cjsw=385e-12 mj=0.51 mjsw=0.36 pb=0.70