LAB 1: Circuit Simulation

1. Objective

The objective of the session is to give you initial exposure to the software environment you will be working on during the course.

You will be using spice3, the circuit simulator, and executing some of the procedures you will be using in the lab and homework assignments during the course.

2. Tasks

a. Make sure your account is correctly setup.

Follow the directions on the handout for setting up your account to operate on the EE141 lab environment (please read ~ee141/INFO/class-setup.ps if you are not familiar with this environment). When you have it correctly set up, you will see the Spice3 prompt when you invoke spice3 from the shell:

% spice3f3

...spice announcement message...

Spice ->

Quit spice for now

Spice -> quit

b. Copy the working files from the ee141 master account to your home directory

% mkdir LAB1

% cd LAB1

% cp ~ee141/LAB1/* .

c. Examine the spice deck for the RTL inverter.

The file RTLinv.cir contains the description of a RTL (Resistor Transistor Logic) inverter. The schematic of the circuit is given in Figure 1.1.

Type the file:

% cat RTLinv.cir

Simple RTL inverter

* netlist

VCC vcc 0 5

VIN in 0 PULSE 0 5 2NS 2NS 2NS 30NS

RB in base 10K

Q1 out base 0 Q1

RC vcc out 1K

* model

.MODEL Q1 NPN BF 20 RB 100 TF .1NS CJC 2PF

* analysis

.TRAN 1NS 30NS

.DC VIN 0 5 .1

.END

There are three main sections in the file:

* The netlist description. Netlist is a designation for a computer readable representation of the schematic of a circuit.

* The models used. A model in spice3 is a description of the parameters of the equations used by spice3 to analyze the circuit.

* The analysis to be performed during the simulation. We are requesting a transient analysis and the DC Transfer characteristic of the circuit

d. Simulate the circuit.

Start spice3 again

% spice3f3

Load the RTLinv circuit

Spice -> source RTLinv.cir

Run the simulation

Spice -> run

e. View the result of the Transient Analysis

Let's examine the transient analysis:

Spice -> setplot

? tran1

Spice -> plot v(in) v(out)

You should be looking now at a diagram representing the voltages at the input and output nodes of the inverter as a function of time.

If you want to look at all nodes, type

Spice -> plot all

f. View the DC Transfer Characteristic

Spice -> setplot

? dc1

Spice -> plot v(out) v(in)

g. Play with spice and quit

Type-in the following commands and see if you can tell what they do:

display, listing, edit, history, quit.

h. Transform the RTL gate into a NMOS inverter with passive load.

We are now going to replace the bipolar transistor by a MOS transistor:

First, we need to obtain the model for the transistor. Look into the EE141 master account lib directory (~ee141/lib). The file scmos.mod contains a description of the models of the MOS devices we will be using in the course. Merge that file with the RTLinv.cir into a new file:

% cat RTLinv.cir ~ee141/lib/scmos.mod > MOSinv.cir

Edit MOSinv.cir. You will need to replace the bipolar transistor with a MOS transistor. Delete the line

Q1 out base 0 Q1

and insert a MOS transistor with area = 2 micron * 10 micron

M1 out base 0 0 NMOS L=2U W=10U

Make sure you move (or comment out) the .END line to the end of the file.

Exit the editor. ( :wq )

i. Simulation and Analysis of the MOS inverter

Repeat steps d to g, this time using MOSinv.cir as the input file.

3. Report

No report is due.

Acknowledgment

This lab was conceived by Prof. Andy Neureuther.