The
objective of this lab is to use MAGIC to layout a CMOS inverter and a NAND
gate. You should be able to fit these layouts within the given area without
any design rule violations. You should also design your gates so that the
connections for V
,
V
,
and GND, as well as the input(s) and the output, all come through
the indicated slots in the templates provided.
b. Layout the CMOS inverter using MAGIC. The circuit diagram of the inverter is shown in Figure 3.1 below. Use a W/L ratio of 3/2 (in lambda) for the NMOS, and 6/2 for the PMOS transistors. State in your report why this is a reasonable size.
The
file inverter.mag contains the template for this layout. To start
you off, the PMOS diffusion has been done for you. Copy this file into
your own account by issuing the following command:
>
cp ~e141/LAB3/Inverter.mag .
and
edit it using MAGIC. Turn in a printout of the complete inverter.
c. In this part, you will be scaling the CMOS inverter to its minimum ratioed size in accordance with the design rules. Observe especially the automatic design-rule-checking feature of MAGIC. Use the same transistor sizes as in part b.
Copy
the files minInverter1.mag, and minInverter2.mag to your
account.
>
cp ~e141/LAB3/minInverter1.mag .
>
cp ~e141/LAB3/minInverter2.mag .
They
contain the layout area that your inverter should fit into. Only add
material within the yellow box. Be sure to draw both wells, as well
as appropriately connected contacts to each well. Actually, the
wells can go outside the box, but nothing else should. Complete both layouts
and print out.
d. Design and layout a two input CMOS NAND gate. Use the template NANDgate.mag for your layout. Remember to copy the file into your account before editing:
>
cp ~e141/LAB3/NANDgate.mag .
Your
NAND gate should fit in the area given in the template. Make all PMOS and
NMOS transistors 6/2. In your write-up, state why you have changed the
size of the NMOS. Print and turn in your layout with your report.
Your
report should contain the transistor schematics of all of your designs,
annotated with the relative transistor sizes. Provide hand calculations
of t
,
t,
and t.
A printout of the layouts should be included. To make the layout more readable,
make sure to label the most important nodes in MAGIC.
This
lab was conceived by Costas Spanos and Andy Burstein.