The
objective of the session is to complete a design using MAGIC, optimize
the layout, and perform circuit extraction. Having done that, you will
simulate the extracted circuit using SPICE. The circuit must be optimized
in order to meet the requested specifications.
b. Extract the SPICE file from the 2-input NAND layout you have designed in Lab 3. To do this, use the extract command in MAGIC. Then use the ext2spice program to convert the extracted file to a SPICE file (Read the ext2spice manual page first).
c. Simulate the extracted circuit to
obtain the DC voltage characteristics (V
= 5 V). Determine the V
,
V
,
V
,
V,
NM,
and NM
from the VTC. To do so for this two-input device, set alternatively one
of the inputs to 5 V and sweep the other one. Is there any difference between
the two VTC's obtained this way? Explain your answer. Compare the SPICE
generated values with the ones you obtained manually.
d. Using MAGIC and SPICE, redesign your
NAND gate such that it has a minimal area, yet meets the specification
that t
and t
< 1.5 nsec, assuming that it is driving an external capacitive load
of 0.25 pF in addition to an identical NAND gate. Extract and simulate
the obtained circuit to demonstrate that it meets the specified timing
requirements.
Note that you must use an editor to modify the generated SPICE file before you can simulate it. You must add the necessary supply voltages, input signals and device models (from ~ee141/lib/scmos.mod). You should also include the necessary command lines to complete the SPICE input deck.
e. Discuss qualitatively how you would design a 4-input NAND gate that meets the same timing requirements.
In
addition to your LAYOUT plots and SPICE input decks, your report should
also include the circuit schematics, the manual calculations, a comparison
between the manual and SPICE calculations (and an explanation of the differences),
as well as a short narrative describing the reasons behind your design
choices in part d.
This
lab was conceived by Costas Spanos and Jan Rabaey.