The
purpose of this lab is to examine the capacitive and resistive parasitics
introduced by interconnections and the various ways to cope with these
parasitic effects to lessen their impact. In doing so, you will try out
some buffering ideas and get a feel for the tradeoffs involved with buffer
design. In order to get more out of this lab, please perform all hand calculations
before entering your lab section!
A
library of buffers is provided in the directory ~ee141/LAB6. The
minimum-sized inverter is also given, and can be found in ~ee141/LAB6/mininverter.mag.
Spend some time getting familiar with the various library components.
b. Extract the input gate capacitance
C
of the minimum-sized inverter. Also, determine its the propagation
delay when driving another minimum-sized inverter, called t
.
In order to accomplish this, use MAGIC, extract the layout, and simulate
it using SPICE.
c. Using the information obatined in b, select those two buffers chosen from the library that drive the output load in the shortest amount of time (in the configuration of Figure 6.1). You may use the same buffer twice.
d. Now, in MAGIC, construct the circuit
you designed in part c, and simulate it. You can drive the first
minimum-sized inverter with a signal that has a 0.1 ns rise and fall time.
The propagation delay of the circuit is from the 50% voltage swing on the
ideal voltage source to the 50% point of V
.
Did your hand calculations match those reported by SPICE? Explain the differences.
For
the report, answer all questions above, and include the hand calculations
and a printout of the magic files for the two-buffer circuit.
e. In reality, resistance is also an
issue when driving such a large capacitance. Consider a series of buffers
distributed across a chip to drive a signal along a total path of 10 mm
of polysilicon (1.8 
m
wide) and then onto an off-chip capacitance of 20 pF (Figure
6.2). Once again, we try to minimize the delay by inserting two buffers,
selected from the library. Note that the design is a mixture of the buffer
and repeater approaches described in your reader.
f. Determine the resistance and the capacitance of the poly wire (use the numbers provided in the reader). Using hand calculations, figure out which buffers to use and where to place them in order to minimize the time required to drive the load capacitance. Remember that the buffers may be placed anywhere along the line of polysilicon. This means that in your design, the sum of the three resistors in Figure 6.2 must equal the total resistance of the poly line.
g. Now, simulate this circuit by extracting
the MAGIC layouts for each of the inverters and constructing the SPICE
file corresponding to Figure 6.2. Introduce the distributed
delay line by using the 
3
model. How well did your hand calculations match the simulated values?
h. Given what you learned comparing your hand calculations with simulated values, play around with the design by substituting different buffers and placing them in different spots along the poly line to see if you can reduce the time further. How does your final design differ from your initial, manually calculated one? In your report, include your initial choice of buffer size and placement, and the results of your experimentation.
Answer
all the questions posed in section 2. Make sure to document your choices
and to include all relevant SPICE listings.
This
lab was conceived by Nelson Chow.