LAB 7: Static RAM

1. Objective

2. Tasks

The layout have been partially flattened from an entire SRAM design for your convenience. The top of the layout contains address latches and drivers, in subcells addrLtc and addrDr respectively. Below them are the row decoders. To the right of the decoders are the word line drivers in subcells rowD. Note that the rightmost address latch/driver does not go to the address decoders; its outputs go to the column decoders in the sensamps, which are not present in these layouts. Below the address drivers, the row of cells called addrTopE, addrTopO, and rowDTop are part of the self-timing circuitry for the SRAM. They function like a "dummy" row decoder, except that their row is always selected, generating an extra word enable signal that is used for timing purposes.

The decoder layouts contain some wires that are not connected to any transistors. These wires do connect to transistors in the whole SRAM, but they're just here to annoy you now. When you extract the circuits, these wires will show up as floating capacitors and will cause spice to complain. The simplest solution is to tie these nodes to ground with voltage sources in spice.

Labels called "obox" are just there for Timlager, the tool that automatically generated the layout. You can ignore them.

b. Examining Address Latches & Drivers

Look at the schematics for the address line driver (Figure 7.1). It consists of a dynamic latch and two dynamic buffers. (Note that precharge is the inverse of eval.) Find and identify these transistors in the magic layout. (Note that M15 is shared by all of the drivers). How do the dynamic buffers differ from the standard dynamic inverter design? Explain its operation. This design was used because the lower supply voltage, coupled with the higher threshold voltage for the pmos devices, accentuates the difference in k' between the NMOS and PMOS devices. Since the PMOS devices have such little current drive, the sram avoids using two PMOS devices in series to drive large capacitances, such as an address line.

c. Examining Decoder Logic

Next, examine the NMOS transistors below the drivers. What is their logical function? Draw a schematic for these devices for the 4 and 8 word layouts. Note the small NMOS devices with their gates connected to the precharge signal. What is their function? Give an example of a situation where their absence would cause an error. Could they be replaced by PMOS devices connected to the eval signal (the inverse of precharge)? What would be the advantages or disadvantages of doing this?

d. SPICE

Perform spice simulations on all three layouts. Use V = 1.5 V and all signal rise/fall times = 5 ns. Have eval and precharge be complements. You might want to run ext2spice with the command line options -s -t -m to get the most convenient nodenames and to merge parallel transistors. Determine the following:

What is the setup time for the address inputs with respect to eval and precharge? Does this change for the different sized decoders?

What is the delay from eval/prech to the address lines changing? to the selected word line changing (assume 100fF load on wordline.) Will the delay be different for different addresses? Will the value of the previous address affect the speed of the next address? Explain.

Derive a model predicting the speed of larger sized decoders based on your simulations. Give an intuitive explanation of your model. What part(s) of the circuit will dominate the speed as the size of the decoder gets larger?

e. Design

This SRAM address decoder was designed to be scalable. For a given sized decoder, you should be able to design a faster one. Your task is to size the transistors in the decoder tree for a 128 row decoder. You will use the same address latch, address driver, and row driver circuits as the current design. You must use either the current tree structured decoder, or a dynamic nand decoder (similar to the tree, but words do not share transistors).
PRIME GOAL: Minimize the propagation delay.

You should NOT layout the entire 128 row decoder. Nor should you simulate the whole decoder with all of its transistors. Since the decoder has a regular structure, you should be able to estimate all of the relevant capacitances and include them in you spice deck as lumped capacitances; in fact, you should estimate the capacitances anyway as a part of you design procedure. (No one in this class would dream of doing the design by trial and error in spice, right?) Only include explicitly include in your simulation enough transistors to make an accurate simulation of as many rows as you feel is necessary. Justify your choice. DOCUMENT YOUR MODEL IN YOUR REPORT.

Provide a floorplan of the intended decoder design. Based on this floorplan, estimate the overall area taken by the decoder.

3. Report

Acknowledgment