EECS 141: FALL 95MIDTERM 1

NMOS:

V = 0.75V, k' = 20 A/V, = 0, = 0.5 V, 2 = -0.6V

PMOS:

V = -0.75V, k' = 7 A/V, = 0, = 0.5 V, 2 = -0.6V

For all problems, you maty assume that the transistor lengths indicated are the effective lengths (L

PROBLEM 1: MOS Inverter

Consider the fictitious gate of Figure 1. The I-V characteristic of the load device L is given in the Figure as well.

a. Determine (W/L) such that a V of 1V is obtained.

b. Write down the equation(s) you would use to solve for V.

c. Find t.

d. Determine the average static power consumption, assuming that the input is high 75% of the time.

f. Figure 2 shows the load-lines of two possible load devices. Determine which one is better (a or b) for each of the following gate properties and explain in ONE line why.

Problem 2: Combinational Logic

The gate below has the advantage of being simple and requiring the minimum number of transistors for the function intended.

a. Derive the boolean expression for F. What logic function does this gate implement?

b. Determine the exact output voltage for each of the following conditions (assume that the supply rails and the logic levels at the inputs are set at 0 V and 3.3 V):

c. Determine t and t between node B and the output for X = 0 and Y = 1. You may assume an equivalent resistance of 10 k for an NMOS transistor and 25 k for a PMOS. The capacitance at nodes m and n equals 100 fF, while node F is loaded with 300 fF.