EECS 141: FALL 95MIDTERM 2

NMOS:

V_Tn = 0.75V, k'_n = 20 A/V², = 0, = 0.5 V^1/2, 2_F = -0.6V

PMOS:

V_Tp = -0.75V, k'_p = 7 A/V², = 0, = 0.5 V^1/2, 2_F = -0.6V

Bipolar NPN:

_F = 100, I_S = 1.E-17 A, _T = 26 mV, V_BE(on) = 0.7 V, V_BE(sat) = 0.8 V, V_CE(sat) = 0.1 V

For all problems, you maty assume that the transistor lengths indicated are the effective lengths (L_eff) or, equivalently, that LD = 0.

In a recent ee141 project, I encountered the following ingeneous dynamic circuit. It claimed to be solving the dynamic cascading problem without needing extra clocks or inverters. For your analysis you may assume that every node in the network represents a 10 fF capacitance, Each output signal (Out1 and Out2) is loaded with an extra 10 fF wiring capacitance. All transistors are minimum size (3/2 for NMOS and 9/2 for PMOS).

a. Determine the intended logic function of the gate.

b. Does this approach indeed solve the cascading problem? Explain your answer.

c. The circuit has two very important problems (besides the potential problem discussed in part b.). Define each problem, quantify it precisely (e.g., if you determine that the power consumption is too high, determine the value of the consumption), and propose a solution for the problem.

Problem 2: BiCMOS

The gate below has the advantage of being simple and reduces the number of bipolar transistors needed.

Determine the size of transistor M₂ such that the gate displays similar values for t_pLH and t_pLH. You may assume that the load capacitance is huge and dominates the performance The bipolar transistor is minimum size, while the size of M₁ equals (W/L)₁. You may assume that the output swings from rail to rail. You may also assume that the MOS transistors stay in saturation during the transients. Solve symbolically - and do NOT fill in any numbers.

Problem 3: Merged CMOS/Bipolar current switch logic

Consider the following circuit.

a. Determine V_OH (V_in= 5 V) and V_OL (V_in = 0 V).

b. Determine the (W/L) of M₁ so that the output is precisely centered in the middle (V_out = V_out) for V_in = 3 V. BE PRECISE.

c. Give one example to illustrate why or where this gate could be useful.

Problem 4: Logic functionality

Determine the logic functions x and y, implemented by the circuit below. Explain the function of the circuitry in the box on the left.

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