EECS 141: FALL 94 - FINAL

NMOS:

V = 0.75V, k' = 20 A/V, = 0.05, = 0.5 V, 2 = -0.6V

PMOS:

V = -0.75V, k' = 7 A/V, = 0.1, = 0.5 V, 2 = -0.6V

Bipolar NPN:

= 100, V() = 0.7V, V() = 0.8V, V() = 0.1V

Wiring:

Aluminum: C = 0.03 fF/m; C = 0.045 fF/m, R = 0.05 /o

Polysilicon: C = 0.06 fF/m; C = 0.045 fF/m, R = 10 /o

For all problems, you maty assume that the transistor lengths indicated are the effective lengths (L

All questions are worth 15 points, except problems 1 and 7 which are graded on 10 points.

PROBLEM 1: Logic Modules

For the logic modules shown below: a) Derive the global logical function b) Describe PRECISELY the logic style which is being employed for the implementation. c) Derive a first-order expression for the delay as a function of the number of input bits N (assuming that extra bits are added in a similar manner).

PROBLEM 2: Memory

A NOR-based EPROM memory is shown in FIG. 1. The following properties of the cell are known: size: 6m x 6m, V of unprogrammed transistor = 1.5 V, V of programmed devices = 7 V, k' = 10 A/V, = 0.05, and (W/L) = (1.8/1.2). Source and drain overlap capacitance of 3 fF, gate capacitance of 8 fF, source and drain diffusion capaictance = 10 fF, bitline/capacitance per cell = 2 fF.

a) Determine the bitline capacitance, assuming that a total of 1000 cells are connected to a single bitline.

b) Determine the size of the pull-up transistor (which is a normal NMOS transistor) such that the voltage swing on the bitline is restricted to 2 V maximum.

c) Assume that cell A is selected and programmed to implement a 0. The sense amplifier needs a drop of 1V on the bitline to trigger. Determine the time is takes before the sense amplifier becomes active.

d) Assume that 50% of the bits in a 1000x1000 memory array are programmed to be a 0 (spread randomly over the complete array). Assume further that the memory address is toggled at a rate of 5 MHz. Determine the static and dynamic power consumption of the array.

PROBLEM 3: LOGIC

Each of the circuits shown has one major problem. Describe a) the intended logic function, b) describe precisely the problem and c) present a technique for solving it.

a)

b)

c)

d)

Problem 4: Interconnect (1)

Bill, a designer fresh from ee141 gets a plush job at Intel, where he is charged to design the output drivers for the latest Pentium processor. His task is to drive a 100 pF capacitance, using only 4 buffer stages. His process has the following parameters: Operating voltage V = 3.3 V, input capacitance of minimum size inverter = 15 fF, all other transistor parameters are given up front. The minimum size NMOS transistor equals (1.8/1.2) and the minimum size PMOS is scaled appropriately to give identical current.

a. Determine the sizing of the buffers such that a minimum delay is obtained.

b. Determine that propagation delay, assuming that during the switching a buffer stage produces a(dis) charging current of the pattern shown in FIG. 2b (you may ignore the channel length modulation, or = = 0).

c. Under the same supposition, determine the maximum value of the voltage bounce on the supply rail, assuming that supply rails are connect to the supply with an inductance of 20 nH.

d. His manager is not too happy about the bounce and decides the following. Bill can double the propagation delay of his driver, but he should minimize the bounce. Describe the strategy Bill should follow to do so and determine approximately the new sizes of the buffer units.

Problem 5: Interconnect (2)

FIG. 3 shows a clock distribution network. Each straight segment of the clock network (between the nodes) is 5mm long, 3m wide, and is implemented in polysilicon. At each of the terminal nodes resides a load capacitance of 100 fF.

a. Determine the average current of the clock driver, given a voltage swing on the clock lines of 5 V and a maximum delay of 5 nsec between clock source and destination node R. For this part, you may ignore the resistance and inductance of the network.

b. Unfortunately the resistance of the polysilicon cannot be ignored. Assume that each straight segment of the network can be modeled as a -network. Draw the equivalent circuit and annotate the values of resistors and capacitors.

c. Determine the dominant time-constant of the clock response at node R.

d. Assume now that the interconnect technology get scaled in the following way: the width of the wires and the oxide thickness decrease with a factor 2, the height of the wire remains constant, while its length doubles. The load capacitance of the fanout decreases with a factor of 2 as well. Determine the speed-up or slow-down. You should use a single wire segment for this analysis (consisting of a straight wire connected to a load).

Problem 6: Timing

For the circuit of FIG. 4, assume a unit delay through the register and logic blocks (i.e. t = t =1). Assume that the registers, which are positive edge-triggered, have a set-up time t of 1. The delay through the multiplexer, t = 2 t.

a. Determine the minimum clock period. Disregard clock skew.

b. Repeat part a, factoring in a positive clock skew: = t' - t = 1.

c. Repeat part a, factoring in a positive clock skew: = t' - t = 4

d. Derive the maximum positive clock skew that can be tolerated before the circuit fails.

e. Derive the maximum negative clock skew that can be tolerated before the circuit fails.

f. Determine the truth of each of the following statements (by encircling T or F). Explain in one sentence why you believe so.

True single phase clock circuits (TSPC) have no problems with clock skew: T or F

Having more interconnect layers can help to lighten the clock skew problem: T or F

The delay between clock driver and register is the most important parameter when examing clock skew: T or F

Clock skew problems can always be eliminated in a 2-phase clock system: T or F

It is a good design practice to route the 2 phases of a clock parallel to each other as much as possible on the chip to reduce skew: T or F

Problem 7: Sequential Circuits

a. A multi-vibrator circuit is shown in FIG. 5. The schmitt-trigger is supposed to have a rail-to-rail swing. You may ignore the propagation delay of the schmitt trigger (or asume that RC >> t,). Draw the waveforms at the nodes V and V, and determine the function of the circuit (bistable, monostable or astable).

b. Derive an expression for the most important timing parameter of the above circuit as a function of the supply voltage, the schmitt-trigger threshold's V V , and the circuit parameters R and C. The nature of the timing parameter depends upon the type of multi-vibrator (e.g. pulse width for a mono-stable, propagation delay for a bi-stable and oscillation period for an astable).