MASSACHUSETTS INSTITUTE OF TECHNOLOGY

Department of Electrical Engineering and Computer Sciences

Analysis and Design of Digital Integrated Circuits (EECS 6.971) - Quiz 1

Problem 1: CMOS Inverter

Consider the inverter shown above. For part (a) - (c) assume V = 0 V.

(a) What are V and V?

(b) Choose the value for W such that V (switching threshold) is 2 V.

(c) Assume the total output load, including parasitic capacitance, on V is 30 fF. Compute t.

For part (d) and (e) use V = 1 V.

(d) What is the threshold voltage of the NMOS device (V)?

(e) Compute the equivalent junction capacitance for the NMOS device for computing the high to low transition (at the output) propagation delay. Use C = .5 fF/mm, C = .5 fF/mm, m = 0.5, and f = 0.6. The layout of the NMOS device is shown below:

Problem 2: Dynamic Logic

Consider the following dynamic logic circuit.

(a) What function is implemented by the circuit above?

(b) Whater are the final voltages on X and Y if A goes high during the evaluate phase while B and C remain low? Assume V = 0 V during pre-charge.

(c) Redo part (b) if C = 10 fF.

(d) If A, B, and C are uncorrelated and have equal probabilities of equalling 0 or 1, calculate the probability Y will make a 0 -> 1 transition.

(e) If the inputs arrive at 10 Mhz, calculate the power consumption of the circuit (assume C=0).

Problem 3: Adiabatic Charging

(a). Consider the simple RC network shown below. The switch is closed at t=0 and v(t=0) = 0.

Compute the total energy dissipated in the resistor to charge the output to V. SHOW YOUR WORK.

(b). An approach to reduce the energy dissipated to charge a capacitor to V is shown below. Once again assume V(t=0)=0

Compute the total energy dissipated in the resistor to charge the output to V.

(c) What would the dissipation be if there are N switches with power supplies equally spaced (V/N, 2V/N, ..., V)?