Digital Integrated Circuits - Table Of Contents (Draft) Digital Integrated Circuits - Table Of Contents (Draft) 
1.1. A Historical Perspective 2 1.2. Issues in Digital Integrated Circuit Design 4 1.3. To Probe Further 13 1.4. Exercises 15
PART I. A CIRCUIT PERSPECTIVE2.1. Introduction 18 2.2. The Diode 19 2.2.1. A First Glance at the Device 19 2.2.2. Static Behavior 22 2.2.3. Dynamic or Transient Behavior 28 2.2.4. The Actual Diode - Secondary Effects 38 2.2.5. The SPICE Diode Model 39 2.3. The MOS(FET) Transistor 41 2.3.1. A First Glance at the Device 42 2.3.2. Static Behavior 43 2.3.3. Dynamic Behavior 50 2.3.4. The Actual MOS Transistor - Secondary Effects 54 2.3.5. SPICE Models for the MOS Transistor 61 2.4. The Bipolar Transistor 67 2.4.1. A First Glance at The Device 68 2.4.2. Static Behavior 70 2.4.3. Dynamic Behavior 78 2.4.4. The Actual Bipolar Transistor - Secondary Effects 85 2.4.5. SPICE Models for the Bipolar Transistor 88 2.5. A Word on Process Variations 91 2.6. Perspective: Future Device Developments 94 2.7. Summary 95 2.8. To Probe Further 96 2.9. Exercises and Design Problems 97
3.1. Introduction 118 3.2. Definitions and Properties 118 3.2.1. Area and Complexity 118 3.2.2. Functionality and Robustness: The Static Behavior 119 3.2.3. Performance: The Dynamic Behavior 126 3.2.4. Power and Energy Consumption 129 3.3. The Static CMOS Inverter 130 3.3.1. A First Glance 130 3.3.2. Evaluating the Robustness of the CMOS Inverter: The Static Behavior 134 3.3.3. Performance of CMOS inverter: The Dynamic Behavior 139 3.3.4. Power Consumption and Power-Delay Product 153 3.3.5. A Look into the Future: Effects of Technology Scaling 158 3.4. The Bipolar ECL Inverter 162 3.4.1. Issues in Bipolar Digital Design: A Case Study 163 3.4.2. The Emitter-Coupled Logic (ECL) Gate at a Glance 167 3.4.3. Robustness and Noise Immunity: The Steady-State Characteristics 173 3.4.4. ECL Switching Speed: The Transient Behavior 180 3.4.5. Power Consumption 191 3.4.6. Looking Ahead: Scaling The Technology 193 3.5. Perspective: Area, Performance and Dissipation 194 3.6. Summary 195 3.7. To Probe Further 196 3.8. Exercises and Design Problems 197
4.1. Introduction 206 4.2. Static CMOS Design 207 4.2.1. Complementary CMOS 207 4.2.2. Ratioed Logic 219 4.2.3. Pass Transistor Logic 228 4.3. Dynamic CMOS Design 241 4.3.1. Dynamic Logic: Basic Principles 241 4.3.2. Performance of Dynamic Logic 244 4.3.3. Noise Considerations in Dynamic Design 246 4.3.4. Cascading Dynamic Gates 250 4.4. Power Consumption in CMOS Gates 254 4.4.1. Switching Activity of a Logic Gate 254 4.4.2. Glitching in Static CMOS Circuits 260 4.4.3. Short-circuit Currents in Static CMOS Circuits 262 4.4.4. Analyzing Power Consumption using SPICE 264 4.4.5. Low Power CMOS Design 266 4.5. Perspective: How to Choose a Logic Style? 273 4.6. Summary 274 4.7. To Probe Further 275 4.8. Exercises and Design Problems 276
5.1. Introduction 292 5.2. Bipolar Gate Design 292 5.2.1. Logic Design in ECL 293 5.2.2. Differential ECL 295 5.2.3. Current Mode Logic 300 5.2.4. ECL with Active Pull-Downs 303 5.2.5. Alternative Bipolar Logic Styles 305 5.3. The BiCMOS Approach 310 5.3.1. The BiCMOS Gate at a Glance 311 5.3.2. The Static Behavior and Robustness Issues 313 5.3.3. Performance of BiCMOS Inverter 316 5.3.4. Power Consumption 321 5.3.5. Technology Scaling 321 5.3.6. Designing BiCMOS Digital Gates 322 5.4. Digital Gallium Arsenide Design * 325 5.4.1. GaAs Devices and their Properties 325 5.4.2. GaAs Digital Circuit Design 331 5.5. Low Temperature Digital Circuits * 336 5.5.1. Low Temperature Silicon Digital Circuits 337 5.5.2. Superconducting Logic Circuits 338 5.6. Perspective: When to Use High-Performance Technologies? 346 5.7. Summary 347 5.8. To Probe Further 348 5.9. Exercises and Design Problems 350
6.1. Introduction 358 6.2. Static Sequential Circuits 358 6.2.1. Bistability 358 6.2.2. Flip-Flop Classification 360 6.2.3. Master-Slave and Edge-Triggered FF's 363 6.2.4. CMOS Static Flip-Flop's 367 6.2.5. Bipolar Static Flip-Flop's 371 6.3. Dynamic Sequential Circuits 373 6.3.1. The Pseudo-Static Latch 374 6.3.2. The Dynamic 2-phase Flip-Flop 375 6.3.3. The C2MOS Latch 377 6.3.4. NORA-CMOS - A Logic Style for Pipelined Structures 381 6.3.5. True Single Phase Clocked Logic (TSPCL) 385 6.4. Non-Bistable Sequential Circuits 389 6.4.1. The Schmitt Trigger 389 6.4.2. Monostable Sequential Circuits 395 6.4.3. Astable Circuits 397 6.5. Perspective: Choosing a Clocking Strategy 401 6.6. Summary 401 6.7. To Probe Further 402 6.8. Exercises and Design Problems 403
PART II. A SYSTEM PERSPECTIVE7.1. Introduction 410 7.2. Datapaths in Digital Processor Architectures 410 7.3. The Adder 412 7.3.1. The Binary Adder: Definitions 412 7.3.2. The Full Adder: Circuit Design Considerations 415 7.3.3. The Binary Adder: Logic Design Considerations 423 7.4. The Multiplier 435 7.4.1. The Multiplier: Definitions 435 7.4.2. The Array Multiplier 436 7.4.3. Other Multiplier Structures 440 7.5. The Shifter 441 7.5.1. Barrel Shifter 442 7.5.2. Logarithmic Shifter 444 7.6. Other Arithmetic Operators 445 7.7. Power Considerations in Datapath Structures 446 7.7.1. Reducing the Supply Voltage 446 7.7.2. Reducing the Effective Capacitance 449 7.8. Perspective: Design as a trade-off 452 7.9. Summary 454 7.10. To Probe Further 455 7.11. Exercises and Design Problems 456
8.1. Introduction 468 8.2. Capacitive Parasitics 468 8.2.1. Modeling Interconnect Capacitance 468 8.2.2. Capacitance and Reliability - Crosstalk 474 8.2.3. Capacitance and Performance in CMOS 476 8.2.4. Capacitance and Performance in Bipolar 492 8.3. Resistive Parasitics 495 8.3.1. Modeling and Scaling of Interconnect Resistance 495 8.3.2. Resistance and Reliability - Ohmic Voltage Drop 499 8.3.3. Electromigration 501 8.3.4. Resistance and Performance - RC Delay 502 8.4. Inductive Parasitics 509 8.4.1. Sources of Parasitic Inductances 509 8.4.2. Inductance and Reliability - Voltage Drop 510 8.4.3. Inductance and Performance - Transmission Line Effects 514 8.5. Some Words On Packaging Technology 526 8.5.1. Package Materials 527 8.5.2. Interconnect Levels 527 8.5.3. Thermal Considerations In Packaging 532 8.6. Perspective: When to Consider Interconnect Parasitics? 533 8.7. Chapter Summary 535 8.8. To Probe Further 535 8.9. Exercises and Design Problems 537
9.1. Introduction 544 9.2. Clock Skew and Sequential Circuit Performance 544 9.2.1. Single-Phase Edge-Triggered 545 9.2.2. Two-Phase Master-Slave 548 9.2.3. Other Clocking Styles 550 9.2.4. How To Counter Clock Skew Problems? 551 9.2.5. Case Study - The Digital Alpha 21164 Microprocessor 554 9.3. Self-Timed Circuit Design* 556 9.3.1. Self-Timed Concept 556 9.3.2. Completion-Signal Generation 559 9.3.3. Self-Timed Signaling 562 9.4. Synchronizers and Arbiters* 567 9.4.1. Synchronizers - Concept and Implementation 567 9.4.2. Arbiters 573 9.5. Clock Generation and Synchronization* 574 9.5.1. Clock Generators 574 9.5.2. Synchronization at the System Level 575 9.6. Perspective: Synchronous versus Asynchronous Design 578 9.7. Summary 579 9.8. To Probe Further 579 9.9. Exercises and Design Problems 581
10.1. Introduction 588 10.2. Semiconductor Memories - An Introduction 588 10.2.1. Memory Classification 588 10.2.2. Memory Architectures and Building Blocks 591 10.3. The Memory Core 596 10.3.1. Read-Only Memories 596 10.3.2. Non-Volatile Read- Write Memories 610 10.3.3. Read-Write Memories (RAM) 615 10.4. Memory Peripheral Circuitry 629 10.4.1. The Address Decoders 629 10.4.2. Sense Amplifiers 635 10.4.3. Drivers/Buffers 642 10.4.4. Timing and Control 643 10.5. Memory Reliability and Yield 645 10.5.1. Signal-To-Noise Ratio 645 10.5.2. Memory yield 649 10.6. Case Studies in Memory Design 651 10.6.1. The Programmable Logic Array (PLA) 652 10.6.2. A 4 Mbit SRAM 655 10.7. Perspective: Semiconductor Memory Trends and Evolutions 657 10.8. Summary 660 10.9. To Probe Further 661 10.10. Exercises and Design Problems 663
11.1. Introduction 672 11.2. Design Analysis and Simulation 672 11.2.1. Representing Digital Data as a Continuous Entity 673 11.2.2. Representing Data as a Discrete Entity 675 11.2.3. Using Higher-Level Data Models 680 11.3. Design Verification 682 11.3.1. Electrical Verification 682 11.3.2. Timing Verification 683 11.3.3. Functional (or Formal) Verification 685 11.4. Implementation Approaches 685 11.4.1. Custom Circuit Design 686 11.4.2. Cell-Based Design Methodology 690 11.4.3. Array-Based Implementation Approaches 698 11.5. Design Synthesis 712 11.5.1. Circuit Synthesis 713 11.5.2. Logic Synthesis 713 11.5.3. Architecture Synthesis 716 11.6. Validation and Test of Manufactured Circuits 718 11.6.1. Test Procedure 719 11.6.2. Design for Testability 720 11.6.3. Test Pattern Generation 730 11.7. Perspective and Summary 733 11.8. To Probe Further 734 11.9. Exercises and Design Problems 736
Back to the top of the page.
Back to the Digital IC home page.