EE241: Advanced Digital Integrated Circuits Spring 2006 MoWe 2:00-3:30pm, 203 McLaughlin

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Project Abstracts

• Subthreshold FinFET for Low Power Circuit Operation: A Study of Sizing and Process Variation on Circuit Functionality, Anupama Bowonder, Pratik Patel
• FIR filter for Ultra Wide-Band Communications, Albert Chang and Rach Liu
• “Platform Based SRAM Sleep Power Minimization”, , Tsung-Te Liu, Yuhui David Chen, Xuening Sun
• Current-Mode Logic, Phillip Chin, Junjie Su, Xiaolan Zhong
• Design of Robust CMOS Logic Circuits for Soft Error Tolerance, Mohammad Amin Arbabian
  Debopriyo Chowdhury
• Limited Switch Dynamic Logic, Josei Chang
• Fault-Tolerant Circuit Design, Animesh Kumar
• Impact of Logic Styles on a Viterbi Decoder in Respect of Performance and Robustness, Ji-Hoon Park and Seung-Bum Suh
• Energy-recovering Adiabatic Logic, Babak Pahlavan, Karl Skucha, Arash Ghanadan
• Self-tuned, Self-timed State Machine Design Using Low Power Pass Transistor Technology, Matthew Pierson
• Dual-Threshold Logic Design, Vincent Ng and Tim Loo
• Design Considerations for Logic Operating in the IC = 1 Regime, Cristian Marcu, Michael Mark, Jesse Richmond
• Sub-Threshold Clock Generation, Khang An Tran, Asako Toda, Anurag Pandit