EE141: Digital Integrated Circuits

Spring 2009

WeFr 2:00-3:30pm, 203 McLaughlin

Professor Jan Rabaey

Course Information

This course is an introduction to digital integrated circuits. The material will cover CMOS devices and manufacturing technology along with CMOS inverters and gates. Other topics include propagation delay, noise margins, power dissipation, and regenerative logic circuits. We will look at various design styles and architectures as well as the issues that designers must face, such as technology scaling and the impact of interconnect. Examples presented in class include arithmetic circuits, semiconductor memories, and other novel circuits.

The course will start with a detailed description and analysis of the core digital design block, the inverter. Implementations in CMOS will be discussed. Next, the design of more complex combinational gates such as NAND, NOR and EXORs will be discussed, looking at optimizing the speed, area, or power. The learned techniques will be applied on more evolved designs such as adders and multipliers. The influence of interconnect parasitics on circuit performance and approaches to cope with them are treated in detail. Substantial attention will then be devoted to sequential circuits, clocking approaches and memories. The course will be concluded with an examination of design methodologies. CAD Tools for layout, extraction, and simulation will be used for assignments, labs and projects.

Homeworks:

Will be posted on the web on Fridays and are generally due the next Friday at 5:00pm in a drop box in 240 Cory.

Homework Information

Discussions:

Discussion sections are optional, but you are encouraged to attend if you have questions about homework, projects, or any concepts you find hard to understand. The section times and locations are listed below. The TAs will provide mini-lectures on topics that many students may not understand at first. These discussions serve as a good supplement to the main lectures.

Discussion Information

Time	Location	TA
Th 4-5pm	400 Cory	TTL
Fr 1-2pm	310 Soda	DC

Laboratory sessions:

There will be 5 labs this semester. Some are hardware and some are software based. It is required that you attend the section you are enrolled in! Lab spaces are limited and often times, students may find that certain computers are not as cooperative as others, so be there on time to get one that works!

Laboratory Information

Time	Location	TA
M 1pm-4pm	353 Cory	DC
Tu 2pm-5pm	353 Cory	TTL/DC
We 11am-2pm	353 Cory	TTL

Textbook:

Text: "Digital Integrated Circuits: A Design Perspective", by Jan Rabaey, Anantha Chandrakasan and Borivoje Nikolic.

Laboratory Manuals: Available on the web-page; handouts provided when necessary.

Class notes Information

Grading Policy:

Homeworks: 10%
Laboratory assignments: 10%
Project: 20%
Midterms (1, 2): 15%+15%
Final Exam: 30%

Exams

Midterm #1: 5th Week (material of lectures 1-7): Wed Febr. 18, 2-3:30pm
Midterm #2: 12th Week (material of lectures 1-20 with emphasis on lectures 8-20): We April 15, 6-7:30pm
Final exam: (material of all lectures with some emphasis on later lectures): Fr May 15, 5-8pm (166 Barrows)

Exam Information