1. Project Description: 8-bit Gray-to-Binary Code Converter.

An n-bit Gray code represents the integers 0 to 2-1 in such a way that the representations for integers i and i+1 differ only in one bit position. An advance from one index to the next adjacent index causes only a single bit to change in value. Note that this property is not true for standard binary codes, as evident in the sequence 00, 01, 10, 11. Gray codes are often used in designs where the multi-bit switches may cause circuit hazards, such as in A/D converters, as well as in designs where low power is desired. Gray encoding is also interesting from a power perspective, as only a single bit changes at a time in a counter application.

To illustrate, consider the decimal sequence 0 through 7. This is expressed in Gray code as 000, 001, 011, 010, 110, 111, 101, 100.

The goal of the project is to minimize the power-delay-product (PDP), or the product of the power and propagation delay for the converter. Remember that the PDP is simply the energy consumed by the logic block per switching event. In doing so, area will only be an issue as far as reducing this quantity is concerned.

2. Implementation and Constraints

Note that for dynamic designs, any duty cycle may be used for the clock, but the clock period should be taken as the propogation delay. At the very worst, no matter which logic family is chosen, the design should have a propogation delay of no more that 30 ns.

POWER SUPPLY: A power supply of 2.0V should be used.

PERFORMANCE METRIC: In order to determine the PDP, measure the total energy consumed by the code converter for the provided set of test inputs. (see below). Remember to include the energy used to switch the inputs and the clock. This combined energy represents the energy needed to convert all the given inputs. From this, the PDP is determined immediately.

V, V: The maximum V , and the minimum V, should settle to within 10% of the final voltage

NOISE MARGINS: The noise margins should be at least 10% of the voltage swing.

LOAD CAPACITANCE: Each output bit of the code converter should have a 200fF load.

INPUTS: The sequence of 20 provided input vectors can be found in ~ee141/INFO/project1/proj1.inputs. These are used to determine the power-delay-product of your design. These input vectors will be fed into your circuit at an interval greater than the worst-case allowable delay. Therefore, static power consumption may be an issue.

3. Layout

Your layout must be free of design rule errors, and must include wells and sufficient contacts to all these wells. Each input, output, and power supply wire should be brought to the edge of your cell with poly, M1, or M2 so that someone using your circuit could make all connections with a single wire for each signal. For example, all power lines should be tied together and brought to the edge of your cell. Try to keep your design as regular as possible since a parameterizable and repetitive design is substantially more successful than a "spaghetti" circuit.

Use common sense in laying out your circuit and remember that long transistors must be built properly!

4. Simulation

5. Report

Remember, a good report is like a good layout: it should perform its function (convey information) in the smallest possible area with the least delay (to the reader) possible.

2 Person Group Project

Due October 24, 1994