UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences

0. One last .cshrc

Before you begin the lab, you need to modify your .cshrc file so that your path can find the xterm command from quasar.cs. Just like last lab, modify your .cshrc so your set path has the new path highlighted in green.   Note that you need all the other stuff as well. 

set path=($path /home/hh/cs152/bin /usr/sww/X11/bin/ /usr/local/mmi_990830/bin.sparc-solaris2 /home/hh/cs152/bin/`arch`)

1. Objectives

There are two primary objectives in this lab. The first objective is to familiarize yourself with SUE (this is the schematic editor). The second objective is to allow you to begin laying out some basic building blocks.

What is SUE all about and why do you should be excited to learn it?
Before we answer this question you must first understand what a schematic is. A schematic is a symbolic representation of your circuit. It abstracts circuit elements such as transistors, capacitors, diodes etc. into symbols. In short, a schematic simplifies your circuit representation into a network of elements you can easily recognize by abstracting away from the layout implementation.
As the semester progresses, you will be doing far bigger and more complex designs then an inverter or a 2 input nand gate. When you start seeing arrays of several hundred transistors in this convoluted amalgamation of polygons and colors, it's nice to have a schematic to guide you through your design and verification.

Sue is a tool which allows you to create schematics. It has powerful features such as cross-probing and layout versus schematic checking (LVS). These are extremely important tools you will be utilizing to verify and debug your future designs. Cross probing in SUE allows you to select a net (a net is basically a wire with some name) in your schematic and see the corresponding net in your MAX layout. Another powerful feature of schematics is hierarchy and abstraction. For example, if you wanted to represent an array of 10 full adder blocks, instead of having a large layout of polygons, you could create a symbol for a full adder, and tile 10 of those blocks together.LVS is a function which uses algorithms to traverse your layout and schematic and make sure they have a one-to-one correspondence. If LVS finds areas that don't match, it will provide output files filled with hints to track your problem down. Another great feature is that you can use the schematics from SUE to document in your report your circuit and clearly annotate things like your critical path. Very Cool.

The objective of this lab is to use first run through the end of the MAX tutorial to learn how to input schematics, and perform cross-probing. After running through the tutorial, copy over the three inverter layouts from ~davewang/lab3/*.max. You should be able to fit these layouts within the given prboundary (the blue net) without any design rule violations. You should also design your gates so that the connections for V_DD and GND, as well as VIN and the VOUT, all come through the indicated slots in the templates provided.

2. Tasks

a). Read Layout Design Rules, pp. 97-103 in the text, to become familiar with the layout design rules used with MAX. Some of the rules may be different, but just keep in mind that the all layers have a minimum length, and that some layers don't like to be too close to each other. Try to make sure that you don't have any DRC errors (little white dots).

b). Layout the CMOS inverter using MAX. The circuit diagram of the inverter is shown in the schematic figure below. Use a W/L ratio of 3/3 (in lambda) for the NMOS, and 4/2 for the PMOS transistors. State in your report why this is a reasonable size.  NOTE:   if you use the gcell instantiation, you will not be able to create the transistor, so it is advisable to do the layout by hand.

So the dimensions for the PMOS are: 4lambda/2lambda
                                              NMOS are: 3lambda/3lambda

The file Inverter.max contains the template for this layout.  Copy this file and all the other necessary files into your own account by issuing the following command:

cp ~davewang/lab3/*.max .
(don't forget the ".")

Edit and complete the inverter using MAGIC. Label the input VIN (make the type "input") and the output VOUT(make the type "output").  Also label Vdd as "Vdd" and make the net global.  Repeat for Gnd.

c). In this part, you will be scaling the CMOS inverter to its minimum ratioed size in accordance with the design rules. Observe especially the automatic design-rule-checking feature of MAGIC. Use the same transistor sizes as in part b.

minInverter1.max and minInverter2.max contain the layout area that your inverter should fit into. Only add material within the prboundary (the blue net). Be sure to draw the nwell(the pwell is implicit in this process), and both the nwell contacts (nwc)and pwel contacts (pwc) as well as appropriately connected contacts to each well. Actually, the wells can go outside the box, but nothing else should. Complete both layouts and print out.

d). After finishing the three layouts (Inverter, minInverter1, minInverter2) go through the rest of the MAX tutorial and familiarize yourself with SUE's interface as well as cross probing. Don't worry about understanding how Latch.max works, just concentrate on the interface and the commands in SUE. Once you have finished the MAX tutorial (the SUE part), generate an Inverter schematic using SUE. Create the schematic called Inverter.sue out of NMOS and PMOS symbols as well as Ground and VDD. Label the input VIN and the output VOUT. Use the cross probing features shown in the SUE to verify that the VIN in the layout corresponds to the VIN in your schematic.

3. Report

Your report should contain the transistor schematics (printed from SUE) of all of your designs, annotated with the relative transistor sizes. Provide hand calculations of t_pLH, t_pHL, and t_p. A printout of the layouts should be included. To make the layout more readable, make sure to label the most important nodes (Vdd, Gnd, VIN, VOUT). Assume Vtn=.43V, Vtp=-.43V VDSATn (for velocity)=.63V VDSATp (for velocity)= -1V kp=115uA/V^2 kn=-30uA/V^2 lambda=0
NOTE: for the report, all layout should contain the grid.