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Course Information

This course is an introduction to digital integrated circuits.  The material will cover CMOS devices and manufacturing technology along with CMOS inverters and gates.   Other topics include propagation delay, noise margins, power dissipation, and regenerative logic circuits.  We will look at various design styles and architectures as well as the issues that designers must face, such as technology scaling and the impact of interconnect.  Examples presented in class include arithmetic circuits, semiconductor memories, and other novel circuits. 

The course will start with a detailed description and analysis of the core digital design block, the inverter. Implementations in CMOS will be discussed.  Next, the design of more complex combinational gates such as NAND, NOR and EXORs will be discussed, looking at optimizing the speed, area, or power. The learned techniques will be applied on more evolved designs such as adders and multipliers.  The influence of interconnect parasitics on circuit performance and approaches to cope with them are treated in detail.  Substantial attention will then be devoted to sequential circuits, clocking approaches and memories.  The course will be concluded with an examination of design methodologies. CAD Tools for layout, extraction, and simulation will be used for assignments, labs and projects.

The EE141 Week at a Glance:

Homeworks:

Will be posted on the web on Thursdays, and are generally due the next Wednesday at 5:00 pm in a drop box in 558 Cory.
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Homework Information

Discussions:

Discussion sections are optional, but you are encouraged to attend if you have questions about homework, projects, or any concepts you find hard to understand.  The section times and locations are listed below.  The TAs will provide mini lectures on topics that many students have a harder time to understand.  They serve as a good supplement to the lectures.

Discussion Information

Laboratory sessions:

There will be between 6 and 8 labs this semester depending on how much time is allotted for the project.  Some are hardware and some are software based.  It is required that you attend the section you are enrolled in!  Lab spaces are limited and often times, students may find that certain computers are not as cooperative as others, so be there on time to get one that works!

Laboratory Information

Head Lab TA: Jason Hu

Textbook:

Text: "Digital Integrated Circuits: A Design Perspective", by Jan Rabaey. The book is available at ASUC and other bookstores.
The text is supplemented with extra notes and new versions of the chapters. These can be found in the Course Notes section.
Laboratory Manuals: Available on the web-page; handouts provided when necessary.

Grading Policy:

Homeworks: 10%
Laboratory assignments: 10%
Project: 20%
Midterms (1, 2): 15%+15%
Final Exam: 30%

Exam Schedule:

Midterm #1:  Tu February 26, 6:30-8:30pm, 105 North Gate, 6th Week (material of lectures 1-10).
Midterm #2:  Th April 11, 6:30-8:30pm, 277 Cory Hall, 11th Week (material of lectures 1-20 with emphasis on lectures 11-20)
Final exam:  Fr May 17, 12:30-3:30pm, TBD, (material of all lectures with some emphasis on later  lectures)
Exam Information and sample exams

Class FAQ