EE241: Advanced Digital Integrated Circuits

Assignments

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Approximately 5 bi-weekly assignments address the material covered in class but not addressed in the design projects. Assignments have to be returned by the assigned time to Alev Burton (558 Cory Hall).
All assignments are posted on this page (no paper copies are provided).

Problem Sets

• Homework 1 (pdf)   due Tuesday, February 22, by 5pm in 558 Cory
• Problem 3 tips: use standard, complementary CMOS with symmetrical sizing (Wp/Wn = 2:1).  Show only one word line with appropriate loading. Problem 4: you can use Chu, Pulfrey paper, JSSC 12/86.
• Homework 2 (pdf) due Friday, March 3, by 5pm, in 558 Cory.
• Homework 3 (pdf) due Tuesday, March 21, by 5pm, in 558 Cory.
  Problem 4 should read: "... when input probabilities P(A=1) = P(B=1) = P(C=1) = P(D=1) equal ..."
• Homework 4 (pdf) due Tuesday, April 11, by 5pm, in 558 Cory.
• Homework 5 (pdf) due Friday, April 28, by 5pm, in 558 Cory.

Models

Modified Models (drain/source area calculation parameter ACM=3 added)

• 0.25 micron CMOS process (TSMC) - Level 49 (BSIM3v3) models
• 0.35 micron CMOS process (TSMC) - Level 49 (BSIM3v3) models

        Original Models

• 0.25 micron CMOS process (TSMC) - Level 49 (BSIM3v3) models
• 0.35 micron CMOS process (TSMC) - Level 49 (BSIM3v3) models

        Other Models

•   0.35 micron CMOS process - Level 49 (BSIM3v3) models
• Slow
• Nominal
• Fast

Manuals

Available software: http://www-inst.eecs.berkeley.edu/software.html

Hspice manuals: http://www-inst.EECS.Berkeley.EDU/usr/pub/HSPICE.docs/