EE241: Advanced Digital Integrated Circuits

Selected Online Papers

Most of the references can be found through California Digital Library under INSPEC databases: http://www.melvyl.ucop.edu. You may need a password if you are accessing the articles from a site outside UC domain.

All documents are in PDF format unless otherwise mentioned.

Scaling Perspectives and Limits

J. Meindl, Low Power Microelectronics: Retrospect and Prospect, Proceedings of the IEEE, April 1995.
B. Davari et al., CMOS Scaling for High Performance and Low Power - The Next Ten Years, Proceedings of the IEEE, April 1995.
A. Masaki, Deep-Submicron warms up to High Speed Logic, IEEE Cicuits and Devices Magazine, November 1992.
S. Borkar, Design challenges of technology scaling. IEEE Micro, vol.19, no.4, p.23-29, July-Aug. 1999.

Circuit Optimization

W.C. Elmore, The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers, Journal of Applied Physics, vol. 19, no. 1, pp. 55-63, January 1948.
J. Rubinstein, M. Horowitz and P. Penfield, Jr., Signal Delay in RC Tree Networks, IEEE Trans. on CAD, vol. CAD-2, no. 3, pp. 202-210, July 1983.
N. Hedenstierna and K.O. Jeppson, CMOS Circuit Speed and Buffer Optimization, IEEE Trans. on CAD, vol. CAD-6, no. 2, pp. 270-281, March 1987.
I.E. Sutherland, R.F. Sproull, Logical Effort: Designing for Speed on the Back of an Envelope, Advanced Research in VLSI, ARVLSI'91, Santa Cruz 1991.
D. Harris, Logical Effort: Designing for Speed on the Back of an Envelope, slides.

High-Speed Logic Families

R.H. Krambeck, C.M. Lee, H.-F. S. Law, High-speed compact circuits with CMOS, IEEE Journal of Solid-State Circuits, vol. SC-17, no. 3, pp. 614-619, June 1982.
N.F. Goncavles, H.J. De Man, NORA: A racefree dynamic CMOS technique for pipelined logic structures, IEEE Journal of Solid-State Circuits, vol. SC-18, no. 3, pp. 261-266, June 1983.
L.G. Heller, W.R. Griffin, J.W. Davis, N.G. Thoma, Cascode Voltage Switch Logic: A differential CMOS logic family, in IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 16-17, San Francisco, CA 1984.
K. Yano, T. Yamanaka, T. Nishida, M. Saito, K. Shimohigashi, A. Shimizu, A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic, IEEE Journal of Solid-State Circuits, vol.25, (no.2), p.388-95, April 1990.
K. Yano, Y. Sasaki, K. Rikino, K. Seki, Top-down pass-transistor logic design, IEEE Journal of Solid-State Circuits, vol.31, no.6, p.792-803. June 1996.
A. Parameswar, H. Hara, T. Sakurai, A swing restored pass-transistor logic-based multiply and accumulate circuit for multimedia applications, IEEE Journal of Solid-State Circuits, vol.31, no.6, IEEE, June 1996. p.804-9.
M. Suzuki, N. Ohkubo, T. Shinbo, T. Yamanaka, A. Shimizu, K. Sasaki, Y. Nakagome, A 1.5-ns 32-b CMOS ALU in double pass-transistor logic, IEEE Journal of Solid-State Circuits, vol.28, no.11, Nov. 1993. p.1145-51.
N. Ohkubo, M. Suzuki, T. Shinbo, T. Yamanaka, A. Shimizu, K. Sasaki, Y. Nakagome, A 4.4 ns CMOS 54*54-b multiplier using pass-transistor multiplexer. IEEE Journal of Solid-State Circuits, vol.30, no.3, March 1995. p.251-7.
R. Zimmermann, W. Fichtner, Low-power logic styles: CMOS versus pass-transistor logic, IEEE Journal of Solid-State Circuits, vol.32, no.7, IEEE, July 1997. p.1079-90.
K.M. Chu, D.L. Pulfrey, Design Procedures for Differential Cascode Voltage Switch Circuits, IEEE Journal of Solid-State Circuits, vol. SC-21, no. 6, pp. 1082-1087, December 1986.
The Test of Time: Clock-Cycle Estimation and Test Challenges for future Microprocessors, Fisher P.D.; Nesbit R., IEEE Circuits and Devices, vol.14, no.2, March 1998. p.37-44. (NO IMAGE)
M. Matsui, et al, A 200 MHz 13 mm/sup 2/ 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme, IEEE Journal of Solid-State Circuits, vol.29, no.12, pp. 1482-1490. Dec. 1994.
O. Takahashi, N. Aoki, J. Silberman, S. Dhong, A 1-GHz logic circuit family with sense amplifiers, IEEE Journal of Solid-State Circuits, vol.34, no.5, p.616-622, May 1999.
M. Mizuno, et al, A GHz MOS adaptive pipeline technique using MOS current-mode logic, IEEE Journal of Solid-State Circuits, vol.31, no.6, pp.784-791, June 1996.
L. McMurchie, S. Kio, G. Yee, T. Thorp, C. Sechen, Output prediction logic: a high-performance CMOS design technique, Proceedings 2000 International Conference on Computer Design, ICCD 2000, pp.247-54, Austin, TX, 17-20 Sept. 2000.

Low-Power Design

A. P. Chandrakasan and R. W. Brodersen, Minimizing power consumption in digital CMOS circuits, Proceedings of the IEEE, no.4, p.498-523, April 1995.
A.P. Chandrakasan, S. Sheng, R.W. Brodersen, Low-power CMOS digital design. IEEE Journal of Solid-State Circuits, vol.27, no.4, p.473-84, April 1992.
T. Kuroda, T. Sakurai, Low-power circuit design techniques for multimedia CMOS VLSIs, Electronics and Communications in Japan, Part 3 (Fundamental Electronic Science), vol.81, no.9, p.67-74. Scripta Technica, Sept. 1998.
D. Liu, C. Svensson, Trading speed for low power by choice of supply and threshold voltages, IEEE Journal of Solid-State Circuits, vol.28, no.1, pp.10-17, Jan. 1993.
T.D. Burd, T.A. Pering, A.J. Stratakos, R.W. Brodersen, "A dynamic voltage scaled microprocessor system," IEEE Journal of Solid-State Circuits, vol.35, no.11, p.1571-80, Nov. 2000.

Arithmetic Building Blocks

A.D. Booth, A Signed Binary Multiplication Technique, Quart. Journ. Mech. and Applied Math, vol. IV, pt. 2, 1951.
L. Dadda, Some schemes for parallel multipliers, Alta Frequenza, 1965.
J. Sklansky, Conditional-sum addition logic, IRE Transactions on Electronic Computers, pp. 226-230, June 1960.
H. Ling, High-Speed Binary Adder, IBM J. Res. Develop, vol.25, no. 3, pp. 156-166, May 1981.
S. Naffziger, A sub-nanosecond 0.5 mm 64 b adder design, 1996 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, pp. 362-363, ISSCC'96, San Francisco,
CA, 8-10 Feb. 1996. Slides

Timing and Synchronization

S.H. Unger, C.-J. Tan, Clocking Schemes for High-Speed Digital Systems, IEEE Transactions on Computers, vol. C-35, no. 10, pp. 880-895, October 1986.
H. Partovi, et al, Flow-through latch and edge-triggered flip-flop hybrid elements. 1996 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 8-10 Feb. 1996.
F. Klass, et al, A new family of semidynamic and dynamic flip-flops with embedded logic for high-performance processors. IEEE Journal of Solid-State Circuits, vol.34, no.5, (1998 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HI, USA, 11-13 June
1998.), May 1999.
B. Nikolic, et al, Sense amplifier-based flip-flop. 1999 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 15-17 Feb. 1999.
V. Stojanovic, V.G. Oklobdzija, Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems. IEEE Journal of Solid-State Circuits, vol.34, no.4, April 1999.
Synchronization in digital system design, D. Messerschmitt, IEEE Journal on Selected Areas in Communications, Oct. 1990.
Micropipelines, I. Sutherland, Communications of the ACM, vol.32, (no.6), June 1989. p.720-38. (NO IMAGE)
Performance of synchronous and asynchronous schemes for VLSI systems, M. Afghahi, C. Svensson, IEEE Transactions on Computers, July 1992.
A fully asynchronous digital signal processor using self-timed circuits, G. Jacobs, R. Brodersen, IEEE Journal of Solid-State Circuits, Dec. 1990.
A PLL clock generator with 5 to 100 MHz of lock range for microprocessor, I. Young et al, IEEE J. Solid State Circuits, vol. 27, no 11, pp. 1599-1607, Nov. 1992
Low-jitter process-independent DLL and PLL based on self-biased techniques, J. Maneatis, IEEE Journal of Solid-State Circuits, vol.31, (no.11), IEEE, Nov. 1996. p.1723-32.

Interconnect and Signaling

Memory Design

Trends in low-power RAM circuit technologies, K. Itoh, K. Sasaki, Y. Nakagome, Proceedings of the IEEE, April 1995.