0.25um ST / Cadence 4.4.3

Design Environment Support

last updated 9/23/99

This is the homepage for developing support of the 0.25um technology for the latest version of Cadence for the BWRC.  Stay tuned as we add stuff.  Note that much of this information is similar but not identical to the Design Environment Support page for the Zabriskie cluster. 

Topics:

• Index of local help pages/files
• Libraries

Index of local help pages/files

General

• Getting Started with HCMOS7 under Cadence 4.4.3
• Cadence FAQ (things you should know)
• LVS Unicad "-nograph" error
• Getting Started with Spectre and OCEAN

In-House Design Tools

• ICMake Tutorial 1: Getting Started with the Simulink Design Flow
• ICMake Help Page
• ICMake with StateFlow Help Page (obsolete)
• BCC Help Page
• SF2VHD Help Page
• Using Stateflow and SF2VHD with the Design Flow
• Simulink Design Flow Parameter Reference
• Logic Verification with m2epic_vec.pl
• Front to Back Logic verification with flow
• Existing Modules Help Page - from SCR1

Synopsys

• Getting Started with Synopsys Sythesis and Simulation Tools

Epic

• Epic Tools Introduction
• Arcadia Parasitic Extraction

Mentor Tools

• Calibre/xCalibre

System Administration

• Sysadmin's Guide to HCMOS 7 and Cadence 4.4.3
• First Looks at Unicad 2.4
• Setting up the Hitz Proxy Server

Libraries

 Outside Libraries

• CORELIB - standard cell library
  • Databook - Guide to the standard cell names and functions
  • Standards - Description of the standards for designing your own standard cells
• IOLIB_80 - I/O pad library
• ugnIO80hcmos7 - a support library for IOLIB_80
• devices_symbols - contains the basic device (active & passive) symbols and pcells
• STlib - contains logical symbols (vdd, gnd, pins)
• st_dk7rev3 - the technology library (all new libraries should attach to this file)
• example - a simple example library

All of these libraries can be added to environment by adding the line "INCLUDE /tools/cds99/local/libraries/st_dk7rev3/cds.lib" to your cds.lib file.

In-House Digital Libraries

• Module Design Manifesto - Requirements for modules to work with the Place & Route and Verification design flows
• Simulink Design Manfesto - Requirements for Simulink models to work with the ICMake design flow
• Module Characterization Flowfdfdsafsdf-Resources on Characterizing the modules
• Module Specifications - The Simulink blocks that need to be generated in modules.
• How to Set up SourceSafe - How to examine the Simulink model which serves as the input to our design flow.
• Logic Verification - How to verify that your HSPICE netlist matches your SIMULINK design.

Naming Conventions

• Naming Conventions - Please follow these rules for naming nodes, cells, and libraries in SCR1.

maintained by Rhett Davis
wrdavis@eecs.berkeley.edu