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Module Functionality Specification Web Page

This page is intended to identify the specifications needed for module generation and design.  The initial components are developed on Simulink and broken down into modules derived from Simulink's Fixed Point Blocksets.

Specifications

Each Simulink model should give enough specification so that the module designer can adequately design the total functionality of the module.   Below are the current list of general design parameters needed by the module designers(Dave, Ben, and Kelvin).

  • Voltage supply should be designed for 1.0 volts.
  • Power - Our primary purpose is to optimize for power.  Considerations such as propagation delay and area are up to the module designers.
  • Number of Bits (dimensions)
  • There will be 3 metal layers used, except for the multiplier.
  • Pinlist Specifications (Location of Pinouts, Functionality, Timing Waveforms)
  • Pipeline Stages??

 

Modules

The modules listed below are what is currently needed for the module design library.   Specifications are given with each model so that the module designers can effectively build functional modules.  Foundamental modules from Simulink libraries will be designed in order to create different modules within a library.  The names of the Simulink blocks should match the names of the modules.  The Simulink library is located in Sourcesafe ($/scr/receiver/digital/structural/fundamental.mdl)

Registers

Module Module Name Parameter Functionality Inputs Outputs Complexity Status/ Certfication(Rhett AND Paul)
Reg Reg data_type

data_scale

T (chip period)

scan_reg (checkbox)

 Stores a real value

IZ[n] = IA[n-1]

If scan_reg = 1, implement scan register

 IA

Enable

 IZ Fundamental Completed   
Reset-able Register Reg_R data_type

data_scale

T  (chip period)

scan_reg

 Stores a real value and has a resetable switch.

IZ[n] = IA[n-1]

IZ = 0 if Reset = 0

If scan_reg = 1, implement scan register

 IA

Enable

Reset

 IZ Fundamental     

Adders

Modules Module Name Parameters Functionality Inputs Outputs Complexity Status Certfication(Rhett AND Paul)
Real Adder Add adder_type - 'Ripple Carry' or 'Carry Bypass'

out_data_type

out_scaling

T  (chip period)

 Adds real values

IZ = IA + IB

 IA

IB

Enable

 IZ Fundamental Completed  
Subtractor Sub adder_type - 'Ripple Carry' or 'Carry Bypass'

out_data_type

out_scaling

T  (chip period)

 Subtracts real values

IZ = IA - IB

IA

Enable

Reset

 IZ Fundamental    
Adder and Subtractor Add_Sub adder_type - 'Ripple Carry' or 'Carry Bypass'

add

out_data_type

out_scaling

T  (chip period)

Adds or Subtracts

If add = 1:

  if Add = 1, IZ = IA + IB

  if Add = 0, IZ = IA - IB

If add = 0:

  If Add = 1, IZ = IA - IB

  If Add = 0, IZ = IA + IB

 IA

IB

Add

 IZ  Fundamental 

MUX

Modules Module Name Parameters Functionality Inputs Outputs Complexity Status Certfication(Rhett AND Paul)
MUX MUX data_type

data_scale

 Multiplexor

If SEL = 1, IZ = IA

If SEL = 0, IZ = IB

 IA

SEL

 IZ Fundamental          

MACS

Modules Module Name Parameters Functionality Inputs Outputs Complexity Status Certfication(Rhett AND Paul)
Multiply and accumulator MAC mult_data_type

mult_scaling

out_data_type

out_scaling

T  (chip period)

 Multiplies and Accumulates

IZ[n] = IA * IB + IZ[n-1]

 IA

IB

Reset

 IZ Fundamental           
Complex mutilply and accumator MAC_C mult_data_type

mult_scaling

out_data_type

out_scaling

T  (chip period)

 Multiplies and Accumulates

IZ[n] = IA * IB - QA * QB + IZ[n-1]

QZ[n] = IA * QB + QA * IB + IZ[n-1]

 IA

QA

IB

QB

Reset

Enable_mult

Enable_acc

 IZ

QZ

 Fundamental    

Multipliers

Modules Module Name Parameters Functionality Inputs Outputs Complexity Status Certfication(Rhett AND Paul)
Multiplier Mult out_data_type

out_scaling

T  (chip period)

 Multiplies real values

IZ = IA * IB

 IA

IB

 IZ Fundamental       
Complex multiplier Mult_C out_data_type

out_scaling

T  (chip period)

 Multiplies complex values

IZ = IA * IB - QA * QB

QZ = IA * QB + QA * IB

 IA

QA

IB

QB

 IZ

QZ

 Fundamental    

Other

Modules Module Name Parameters Functionality Inputs Outputs Complexity Status Certfication(Rhett AND Paul)
Comparator Comp data_type

data_scale

 Compare A and B

If A > B, Z = 1

If A < B, Z = 0

 A

B

 Z

Fundamental

        
2's Complement Neg none Z = -A A Z

Fundamental

    
3-bit input Variable Shifter Var_3Shift var_step

data_type

data_scale

 Shift A right by Shift * var_step bits and truncate A

Shift

 Z Fundamental    
2-bit input Variable Shifter Var_2Shift var_step

data_type

data_scale

 Shift A right by Shift * var_step bits and truncate A

Shift

 Z Fundamental    

** The column labeled 'Complexity' are the fundamental modules that will be placed in the Simulink library.  Modules labeled 'Complex' are blocks that will be need but can be built using various fundamental blocks.

Links

  • The Module Design Manifesto web page explains the constraints  placed on the Cadence schematics and layout for modules to ease the design flow.
  • IC design flow meetings have been taken so that others can stay abreast on what has transpared.

 

 

Maintained by Paul Husted
phusted@eecs.berkeley.edu