J. Encarnacao and J, Rabaey, Eds, "Mobile Communications: Technology, tools, applications, authentication and security," Kluwer Academic Publishers, 1996.
J. Rabaey, "Digital Integrated Circuits: A Design Perspective", Prentice Hall, 1996.
J. Rabaey and M. Pedram, Eds, "Low Power Design Methodologies", Kluwer Academic Publishers, 1996.
V. George and J. Rabaey, "Low-Energy FPGAs," Kluwer Academic Publishers, 2001.
M. Pedram and J. Rabaey, Eds, "Power-Aware Design Methodologies," Kluwer Academic Publishers, 2002.
S. Roundy, P. Wright and J.M. Rabaey, "Energy Scavenging for Wireless Sensor Networks," Kluwer Academic Publishers, 2003.
J. Rabaey, A. Chandrakasan and B. Nikolic, "Circuitos Integrados Digitales", 2e Edicion, Pearson Prentice Hall, 2004.
W. Weber, J.M. Rabaey and E. Aerts, Eds, "Ambient Intelligence," Springer-Verlag, 2005.
B. Otis and J. Rabaey, "Ultra-low Power Wireless Technologies for Sensor Networks", Springer-Verlag, 2007.
H. De Man, J. Rabaey, G. Arnout and J. Vandewalle, "Practical implementation of a general computer aided design technique for switched capacitor circuits", Published in "Analog MOS Integrated Circuits", New York, IEEE Press, 1980.
H. De Man, J. Vandewalle and J. Rabaey, "Simulation of sampled data MOSLSI circuits", NATO ASI Conference on computer aids for VLSI-circuits, Urbino, Italy, July 1980, published by Sijthoff & Noordhoff, E 48, pp. 241-284.
J. Rabaey, "A Unified Computer Aided Design technique for Switched capacitor Systems in the Time and the Frequency Domain", PhD. Dissertation, Katholieke Universiteit Leuven, April 1983.
S. Pope, J. Rabaey and R. Brodersen, "Automated design of signal processors using macrocells", in "VLSI Signal Processing", New York, IEEE Press 1984, pp. 239-251.
H. De Man, J. Rabaey, P. Six, "CATHEDRAL II : A Synthesis and Module Generation System for Multiprocessor Systems on a Chip", NATO Advanced Study Institute on Logic Synthesis and Silicon Compilation for VLSI Design, L'Aquila, 1986, in Design Synthesis for VLSI Circuits, Martinus Nijhoff Publishers, Dordrecht.
S. Pope, J. Rabaey and R. Brodersen, "Automatic Generation of Digital Signal Processing Circuits" NATO Advanced Study Institute on Logic Synthesis and Silicon Compilation for VLSI Design, L'Aquila, 1986,in Design Synthesis for VLSI Circuits, Martinus Nijhoff Publishers, Dordrecht.
J. Rabaey, H. De Man, J. Vanhoof, G. Goossens and F. Catthoor,"CATHEDRAL-II : A Synthesis System for Multiprocessor DSP Systems", in "Silicon Compilation", Addison-Wesley, December 1987.
W. Koh, A. Yeung, P. Hoang and J. Rabaey, "A Multi-Processor System for DSP Behavioral Simulation", in VLSI Signal Processing III, IEEE Press, pp. 295-306, November 1988.
J. Rabaey, T. Stoelzle, D. Chen, S. Narayansswamy, R. Brodersen, H. Murveit and A. Santos,"A Large Vocabulary Real Time Connected Speech Recognition System", in VLSI Signal Processing III, IEEE Press, pp 61-74, November 1988.
S. Lee and J. Rabaey, "Interactive Floorplanning", in Anatomy of a Silicon Compiler, Kluwer Academic Publishers, pp 103-126, Fall 1992.
P. Hilfinger and J. Rabaey, "DSP Specification Using the Silage Language", in Anatomy of a Silicon Compiler, Kluwer Academic Publishers, pp. 199-220, Fall 1992.
J. Rabaey, C. Chu, P. Hoang and M. Potkonjak, "Synthesis of Datapath Architectures", in Anatomy of a Silicon Compiler, Kluwer Academic Publishers, pp. 221-250, Fall 1992.
M. Potkonjak and J. Rabaey, "Exploring the Algorithmic DEsign Space using High Level Synthesis", in "High Level Synthesis", by M. Bayoumi, Kluwer Academic, December 1993.
J. Rabaey, "Low Power Digital Design," Circuits and Systems Tutorials, Ed. Chris Toumazou, pp 373-386. LTP Electronics, Oxford, UK, June 1994.
R. Mehra, D. Lidsky, A. Abnous, P.E. Landman, J. Rabaey, "Algorithm and Architecture Level Methodologies," Low Power Design Methodologies, J. Rabaey and M. Pedram, Ed., Kluwer Academic Publishers, Boston, 1996.
J. Rabaey, M. Pedram and P. Landman, "Low Power Design Methodologies - Introduction", Low Power Design Methodologies, J. Rabaey and M. Pedram, Ed., Kluwer Academic Publishers, Boston, 1996.
D. Lidsky, J. Rabaey, "Low-Power Design of Memory Intensive Functions Case Study: Vector Quantization," in Low Power CMOS Design, A. Chandrakasan and R. Brodersen, Ed., pp. 433-436, IEEE Press, 1998.
P. Landman and J Rabaey, "Activity Sensitive Architectural Power Analysis", in Low Power CMOS Design, A. Chandrakasan and R. Brodersen, Ed., pp.516-532, IEEE Press, 1998.
R. Mehra, L. Guerra, J. Rabaey, "Exploiting Locality for Low-Power Design," in Low Power CMOS Design, A. Chandrakasan and R. Brodersen, Ed., pp.574-577, IEEE Press, 1998.
A. Chandrakasan, M. Potkonjak, J. Rabaey and R. Brodersen, "Hyper-LP: A System for Power Minimization Using Architectural Transformations," in Low Power CMOS Design, A. Chandrakasan and R. Brodersen, Ed., pp.578-581, IEEE Press, 1998.
J. Rabaey et al, "Hybrid Reconfigurable Processors —The Road to Low-Power Programmable Computing", Book Chapter, T. Sakurai Editor, Realize, Inc, Japan.
A. Abnous, H. Zhang, M. Wan, G. Varghese, V,. Prabhu, and J. Rabaey, "The Pleiades Architecture," in The Application of Programmable DSPs in Mobile Communications, A. Gatherer and A. Auslander, Ed., Wiley, 2002, pp. 327-360.
H. De Man and J. Rabaey, "System Design and Analysis Overview," in The Best of ICCAD, 20 Years of Excellence in Computer-Aided Design, A. Kuehlman Ed., Kluwer Academic Publishers, 2003, pp. 93-106
G. Goossens, J. Rabaey, J. Vandewalle and H. De Man, "An efficient microcode-compiler for custom DSP-processors", in The Best of ICCAD, 20 Years of Excellence in Computer-Aided Design, A. Kuehlman Ed., Kluwer Academic Publishers, 2003, pp. 107-116.
A. Chandrakasan, M. Potkonjak, J. Rabaey and R. Brodersen, "Hyper-LP: A System for Power Minimization Using Architectural Transformations," in The Best of ICCAD, 20 Years of Excellence in Computer-Aided Design, A. Kuehlman Ed., Kluwer Academic Publishers, 2003, pp. 117-127.
J. Rabaey, "System-on-a-Chip Challenges in the Deep-Submicron Era - A case for the network-on-a-Chip", in Interconnect-Centric Design for Advanced SOC and NOC, Kluwer Academic Publishers, Editor Jari Nurmi, 2004, pp. 3-24.
B.P. Otis, Y.H. Chee, R. Lu, N.M. Pletcher, S. Gambini†, J.M. Rabaey, "Highly Integrated Ultra-Low Power RF Transceivers for Wireless Sensor Networks", in Low-Power Electronics Design, Editor C.Piguet, CRC Press, 2005.
Brian Otis, Nathan Pletcher, Shailesh Rai, and Jan Rabaey, "Low Power Techniques for Wireless Sensing", in Advances in Analog Circuit Design, Springer Press, Nov 2006.
M. Copeland and J. Rabaey, "A dynamic amplifier for MOS-technology", IEE Electronic Letters, Vol. 15, pp. 301-302, May 1979.
H. De Man, J. Rabaey, G. Arnout and J. Vandewalle, "Practical implementation of a general computer aided design technique for switched capacitor circuits", IEEE Journal of Solid State Circuits, Vol. SC-15, pp. 190-200, April 1980.
J. Vandewalle, H. De Man and J. Rabaey, "The adjoint switched capacitor network and its application to frequency, noise and sensitivity analysis", Circuit Theory and Applications, Vol. 9, pp. 77-88, January 1981.
J. Vandewalle, H. De Man and J. Rabaey, "Time, frequency and z-domain modified nodal analysis of switched capacitor networks", IEEE Transactions on Circuits and Systems, Vol. CAS-28, pp. 186-195, March 1981.
J. Vandewalle, J. Rabaey, W. Vercruysse and H. De Man, "Computer aided distortion analysis of switched capacitor filters in the frequency domain", IEEE Journal of Solid State Circuits, Vol. SC-18, pp. 324-333, June 1983.
L. Claesen, H. De Man, J. Vandewalle and J. Rabaey, "DIANA-SC : a versatile top-down analysis tool for switched capacitor circuits", Microelectronics Journal, Vol. 14, Nr. 2, pp. 37-53, 1983.
J. Rabaey, S. Pope and R. Brodersen, "An integrated automated layout generation system for DSP circuits", IEEE Transactions on CAD, Vol. CAD-4, pp. 285-296, July 1985.
H. De Man, J. Rabaey, P. Six, L. Claesen, "CATHEDRAL-II : A Silicon Compiler for Digital Signal Processing Multiprocessor VLSI Systems", Design & Test of Computers, pp. 13-25, December 1986.
F. Catthoor, J. Rabaey, G. Goossens, J. Van Meerbergen, R. Jain, H. De Man, J. Vandewalle, "Architectural Strategies for an Application Specific Synchronous Multi-processor Environment", IEEE Transactions on Acoustics, Speech and Signal Processing, pp. 265-284, February 1988.
H. De Man, J. Rabaey, J. Vanhoof, G. Goossens, P. Six and L. Claesen, "CATHEDRAL-II - a computer-aided synthesis system for digital signal processing VLSI systems", Computer-Aided Engineering Journal, pp 55-66, April 1988.
J. Decaluwe, J. Rabaey, J, Van Meerbergen and H. De Man, "Interprocessor Communication in Synchronous Multi-Processor Digital Signal Processing Chips", IEEE Transactions on Acoustics, Speech and Signal Processing, pp. 1816-1828, December 1989.
G. Goossens, J. Rabaey, H. De Man and J. Vandewalle, "An efficient microcode-compiler for custom DSP-processors", IEEE Journal on Computer Aided Design, vol 9, No 9, pp. 925-937, September 1990.
A. Stolzle, S. Narayanaswamy, H. Murveit, J. Rabaey and R. Brodersen, "Integrated Circuits for a Real Time Large Vocabulary Continuous Speech Recognition System", IEEE Journal on Solid State Circuits, VOL. 26, No 1, Jan. 1991.
C. Shung, R. Jain, P. Hilfinger, J. Rabaey and R. Brodersen, "An Integrated CAD System for Algorithmic Specific IC Design", IEEE Journal on Computer Aided Design, Vol. 10, No 4, pp 447-463, April 1991.
D. Chen, R. Yu, J, Rabaey and R. Brodersen, "A VLSI Gramar Processing SubSystem for a Real-Time Large-Vocabulary Continuous Speech Recognition System", IEEE Journal on Solid State Circuits, VOL. 26, No 3, pp. 443-448, March 1991.
J. Rabaey, C, Chu, P. Hoang and M. Potkonjak, "Fast Prototyping of Datapath-Intensive Architectures", IEEE Design and Test of Computers, pp. 40-51, June 1991.
M. Potkonjak and J. Rabaey, "Allocation, Assignment and Scheduling Algorithms for Hierarchical Data Control Flow Graphs", International Journal on Circuit Theory and Applications, April 1992.
D. Chen and J. Rabaey, "A Reconfigurable Multiprocessor IC for Rapid Prototyping of Algorithmic Specific, High Speed DSP Data Paths", IEEE Journal of Solid State Circuits, Vol. 27, No 12, pp 1895-1904, December 1992.
P. Hoang and J. Rabaey, "Partitioning of DSP Programs onto Multi-processors for Maximum Throughput", IEEE Transactions on Signal Processing, pp. 2225-2235, Vol. 41, No 6, June 1993.
M. Potkonjak and J. Rabaey, "Optimizing the Resource Utilization Using Transformations", IEEE Transactions on Computer Aided Design, vol. 13, No 3, pp. 277-292, March 1994.
J. Rabaey and M. Potkonjak, "Estimating Implementation Bounds for Real Time Application Specific Circuits", IEEE Transactions on Computer Aided Design, vol. 13, No 6, pp. 669-683, June 1994.
M. Potkonjak and J. Rabaey, "Optimizing Throughput and Resource Utilization using Pipelining: a Transformation Based Approach", VLSI Signal Processing Journal, vol. 8, pp 117-130, Oct. 1994.
J. Rabaey, P. Landman, R. Mehru and D. Lidsky, "A High Level Low Power Design Methodology", Nikei MicroElectronics Journal (In Japanese), Nov. 1994.
I. Verbauwhede and J. Rabaey, "Real Time System Design: Solutions and Challenges", VLSI Signal Processing Journal, vol. 9 - no 1-2, pp. 67-88, January 1995.
A. Chandrakasan, M. Potkonjak, J, Rabaey and R. Brodersen, "Optimizing Power using Transformations", IEEE Transactions on Computer Aided Design, vol. 14, No 1, pp. 12-31. January 1995.
D. Singh, J. Rabaey, M. Pedram et al., "Power-conscious CAD tools and methodologies - A Perspective," Proceedings of the IEEE, vol. 83 - no 3, pp. 570-594, April 1995.
P. Landman and J. Rabaey, "Architectural Power Analysis: The Dual Bit Type Method," IEEE Trans. on VLSI Systems, Vol. 3, No. 2, pp. 173-187, June, 1995.
S. Narayanaswamy et al., "A low-power lightweight unit to provide ubiquitous access - application and network support for Infopad", IEEE Journal on Personal Communications,, Vol. 3. (no 2), pp. 4-17, April 1996.
P. Landman and J Rabaey, "Activity Sensitive Architectural Power Analysis", IEEE Transactions on CAD, Vol. 15, No 6, pp. 571-587, June 1996.
P. Landman, R. Mehra, J. Rabaey, "An Integrated CAD Environment for Low Power Design," IEEE Design and Test of Computers, vol 13., No 2, pp. 72-82, June 1996.
Corazao, M.R.; Khalaf, M.A.; Guerra, L.M.; Potkonjak, M, and J. Rabaey, "Performance optimization using template mapping for datapath-intensive high-level synthesis", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.15, (no.8):877-88., Aug. 1996.
Mehra, R.; Guerra, L.M.; Rabaey, J.M. " Low-power architectural synthesis and the impact of exploiting locality", Journal of VLSI Signal Processing, , vol.13, (no.2-3):239-58, Aug.-Sept. 1996.
Verbauwhede, I.; Scheers, C.; Rabaey, J.M, "Analysis of multidimensional DSP specifications," IEEE Transactions on Signal Processing, , vol.44, (no.12):3169-74, Dec. 1996.
R. Mehra, L. Guerra, J. Rabaey, "A partitioning scheme for optimizing interconnect power," IEEE Journal of Solid-State Circuits, V32, pp. 433-443, March 1997.
J. Rabaey, R. Brodersen, W. Gass, and T. Nishitani, "VLSI Design and Implementation Fuels the Signal-Processing Revolution," IEEE Signal-Processing Magazine, pp. 22-38, Jan 98.
D. Lidsky and J. Rabaey, "The Conceptual-Level Design Approach to Complex Systems," Journal of VLSI Signal Processing, vol. 18, No 1, pp. 11-24, January 1998.
L. Guerra, M. Potkonjak, and J. Rabaey, "Behavioral Synthesis of Heterogeneous BISR Reconfigurable ASICs," IEEE Transactions on VLSI Systems, vol. 6 No 1, pp158-167, March 1998.
Potkonjak, M.; Rabaey, J.M., "Algorithm selection: a quantitative optimization-intensive approach", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.18, (no.5), p.524-32, IEEE, May 1999.
Potkonjak, M.; Rabaey, J.M., “Maximally and arbitrarily fast implementation of linear and feedback linear computations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.19, (no.1), IEEE, Jan. 2000, pp.30-43.
H. Zhang, V. George, J. Rabaey, “Low-swing On-chip Signaling Techniques: Effectiveness and Robustness,” IEEE Transactions on VLSI Systems, vol. 8 (no.3), IEEE, June 2000, pp. 264-272.
J. Rabaey, J. Ammer, J. da Silva, D. Patel, S. Roundy, “Picoradio Supports Ad-hoc Ultra-low Power Wireless Networking”, Cover Article, IEEE Computer Magazine, July 2000.
H. Zhang, V. Prabhu, V. George, M. Wan, M. Benes, A. Abnous, and J. Rabaey, “A 1 V Heterogeneous Reconfigurable Processor IC for Baseband Wireless Applications,” IEEE Journal on Solid State Circuits, November 2000
K. Keutzer, S. Malik, R. Newton, J. Rabaey and A. Sangiovanni-Vincentelli, “System Level Design: Orthogonalization of Concerns and Platform-Based Design,” IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol.19, no.12, Dec. 2000, pp.1523-43.
R. Bryant, T. Cheng, A. Kahng, K. Keutzer, W. Maly, R. Newton, L. Pileggi, J. Rabaey, and A. Sangiovanni-Vincentelli, “Fundamental Limits in Design Technology”, Proceedings of the IEEE, vol.89, no.3, March 2001, pp.341-65.
Wan M, Hui Zhang, George V, Benes M, Abnous A, Prabhu V, Rabaey J., "Design methodology of a low-energy reconfigurable single-chip DSP system", Journal of VLSI Signal Processing, vol.28, no.1-2, May-June 2001, pp.47-61.
B.P. Otis an J.M. Rabaey, "A 300 uW 1.9GHz CMOS Oscillator Utilizing Micromachined Resonators," IEEE Journal on Solid State Circuits, July 2003.
Shad Roundy, Paul K. Wright, and Jan Rabaey, "A study of low level vibrations as a power source for wireless sensor nodes," Computer Communications, 26(11):1131-1144, July 2003.
K. Sarrigeorgidis and J.M. Rabaey, “Ultra low power CORDIC processor for wireless communication algorithms,” Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, vol. 38, no. 2, pp. 115-130, September 2004.
Roundy, S.; Leland, E.S.; Baker, J.; Carleton, E.; Reilly, E.; Lai, E.; Otis, B.; Rabaey, J.M.; Wright, P.K.; Sundararajan, V, "Improving power output for vibration-based energy scavengers," IEEE Pervasive Computing Journal, , Volume 4, Issue 1, pp. 28-36, Jan.-March 2005.
H. Qin, Y. Cao, D. Markovic, A. Vladimirescu, and J.M. Rabaey, “Standby supply voltage minimization for deep sub-micron SRAM,” Microelectronics Journal, vol. 36, no. 9, pp. 789-800, July 2005.
Rabaey, J.M.; De Bernardinis, F.; Niknejad, A.M.; Nikolic, B.; Sangiovanni-Vincentelli, A., "Embedding mixed-signal design in systems-on-chip," Proceedings of the IEEE, Volume 94, Issue 6, June 2006 Page(s):1070 - 1088.
Petrovic, D.; Ramchandran, K.; Rabaey, J., "Overcoming untuned radios in wireless networks with network coding," Information Theory, IEEE Transactions on Volume 52, Issue 6, June 2006 Page(s):2649 - 2657.
Rabaey, J.; Ammer, J.; Otis, B.; Burghardt, F.; Chee, Y.H.; Pletcher, N.; Sheets, M.; Qin, H.; "Ultra-low-power design," IEEE Circuits and Devices Magazine, Volume 22, Issue 4, July-Aug. 2006 , Page(s):23 - 29.
Chee, Y.H.; Niknejad, A.M.; Rabaey, J.M., "An Ultra-Low-Power Injection Locked Transmitter for Wireless Sensor Networks," Solid-State Circuits, IEEE Journal of, Volume 41, Issue 8, Aug. 2006 Page(s):1740 - 1748.
H. De Man, J. Rabaey, G. Arnout "On the simulation of switched capacitor filters and convertors using the DIANA-program", Proceedings ESSCIRC 79, pp. 131-133, Southampton, September 1979.
H. De Man, J. Rabaey, G. Arnout and J. Vandewalle, "DIANA as a mixed mode simulator for MOSLSI sampled-data circuits", Proceedings IEEE ISCAS-conference, pp. 435-438, Houston, April 1980.
J. Vandewalle, H. De Man and J. Rabaey, "The adjoint switched capacitor network and its applications", Proceedings IEEE ISCAS-conference, pp. 1031-1034, Houston, April 1980.
J. Vandewalle, H. De Man and J. Rabaey, "A Unified theory for the computer aided analysis of general switched capacitor networks", Proceedings ECCTD Conference, pp. 147-152, Warsaw, September 1980.
J. Rabaey, J. Vandewalle and H. De Man, "On the frequency domain analysis of switched capacitor circuits including all parasitics", Proceedings IEEE ISCAS Conference, pp. 868-871, Chicago, April 1981.
J. Rabaey, L. Claesen, H. De Man and J. Vandewalle, "An overview of CAD techniques for switched capacitor networks", Proceedings of the ECCTD Conference, pp. 513-517, The Hague, August 1981.
H. De Man, J. Rabaey, L. Claesen and J. Vandewalle, "DIANA-SC : A complete CAD-system for switched capacitor filters", Proceedings ESSCIRC Conference, pp. 130-133, Freiburg, September 1981.
J. Vandewalle, H. De Man, J. Rabaey and L. Claesen, "A pictoral derivation of the signal processing mechanisms of multiphase switched capacitor circuits", Proceedings IEEE ISCAS Conference, pp. 25-28, Rome, Italy, May 1982.
J. Vandewalle, J. Rabaey, W. Vercruysse and H. De Man, "Computer aided distortion analysis of switched capacitor filters in the frequency domain", Proceedings ESSCIRC Conference, pp. 37-40, Brussels, September 1982.
J. Rabaey, J. Vandewalle and H. De Man, "A general and efficient noise analysis technique for switched capacitor filters", Proceedings of the IEEE ISCAS Conference 1983, pp. 570-573, Newport, May 1983.
J. Rabaey, S. Pope and R. Brodersen, "An Integrated Automated Layout Generation System for Digital Signal Processing Circuits", Proceedings IEEE CICC Conference 1985, pp. 217-220, Portland, May 1985.
J. Rabaey and R. Brodersen, "Experiences with automated design of audio band DSP circuits", Proceedings IEEE ICASSP Conference, pp. 1541-1544, Tokyo, April 1986.
G. Goossens, J. Rabaey, F. Catthoor, J. Vanhoof, R. Jain, H. De Man, J. Vandewalle, "A computer-aided design methodology for mapping DSP algorithms onto custom multiprocessor architectures", Proceedings of the ISCAS'86 Conference, Vol. 3 of 3, pp. 924-926, San Jose, May 1986.
F. Catthoor, J. Rabaey, G. Goossens, J. Van Meerbergen, R. Jain, H. De Man, J. Vandewalle, "General Datapath, Controller and Inter-communication Architectures of a Dedicated Multi-processor Environment", Proceedings of the ISCAS'86 Conference, Vol. 2 of 3, pp. 730-732, San Jose, May 1986.
P. Six, L. Claesen, J. Rabaey, H. De Man, "An Intelligent Module Generator Environment", Proceedings of the 23nd Design Automation Conference, pp. 730-735, Las Vegas, July 1986.
P. Ruetz, R. Jain, C. Shung, J. Rabaey, G. Jacobs & R. Brodersen, "Automatic layout generation of real-time digital image processing circuits", Proceedings IEEE CICC Conference 1986, pp. 111-115, Rochester, May 1986.
J. Rabaey, J. Vanhoof, G. Goossens, F. Catthoor, H. De Man, "Cathedral II : Computer Aided Synthesis of Digital Signal Processing Systems", IEEE CICC Conference, Portland, pp.157-160, May 1987.
J. Vanhoof, J. Rabaey, H. De Man, "A Knowledge-based CAD System for Synthesis of Multi-processor Digital Signal Processing Chips", Proceedings IFIP Int. Conf. VLSI-87, Vancouver, pp. 41-56, August 1987.
J. Rabaey and H. De Man , "Computer Aided Design of Digital Signal Processing Systems : the IMEC view", IEEE ICCD-Conference, Port Chester, pp. 134-137, October 1987.
H. De Man, J. Rabaey, P. Six, L. Claesen, "Computer Aided Synthesis of Digital Signal Processing ASICs", Proceedings Journees d'Electronique, Lausanne, pp. 121-137, October 1987.
G. Goossens, J. Rabaey, J. Vandewalle and H. De Man, "An efficient microcode-compiler for custom DSP-processors", IEEE ICCAD-Conference, Santa Clara, pp. 24-27, November 1987.
G. Goossens, D. Lanneer, J. Vanhoof, J, Rabaey, J. Van Meerbergen and H. De Man, "Optimization based synthesis of multi-processor chips for signal processing with CATHEDRAL-II", Proceedings International Workshop on Logic and Architecture Synthesis for Silicon Compilers, Elsevier Science Publishers, 1988.
C. Shung, J. Rabaey, R. Brodersen et all, "An Integrated CAD System for Algorithmic-Specific IC Design", Proceedings IEEE Conference on Systems Design, Hawaii, January 1989.
A. Stoelzle, S. Narayanaswamy, K. Kornegay, J. Rabaey and R. Brodersen, "A VLSI Word Processing Subsystem for a Real Time Large Vocabulary Continuous Speech Recognition System", Proceedings IEEE CICC Conference, San Diego, May 1989.
H. Murveit, J, Rabaey et all, "Real Time Large Vocabulary Continuous Speech Recognition", Proceedings IEEE ICASSP Conference, Glasgow 1989.
W. Koh, A. Yeung, P. Hoang and J, Rabaey, "A Configurable MultiProcessor System For DSP Behavioral Simulation", Proceedings IEEE ISCAS Conference, Portland 1989.
F. Catthoor, J. Rabaey and H. De Man, "Target Architectures in The Cathedral Synthesis Environment", Proceedings IEEE ISCAS Conference, Portland 1989.
M. Potkonjak and J. Rabaey, "A Scheduling and Resource Allocation Algorithm for Hierarchical Flow Graphs", Proceedings of the IEEE Design Automation Conference, Las Vegas 1989.
R. Brodersen and J. Rabaey, "Evolution of Microsystem Design", Proceedings ESSCIRC Conference, Vienna, September 1989.
C. Chu, M. Potkonjak, M. Thaler and J. Rabaey, "HYPER : An Interactive Synthesis Environment for High Performance Real Time Applications", Proceedings of the IEEE ICCD Conference, pp 432-435, Boston, October 1989.
Zegers, J.; Six, P.; Rabaey, J.; De Man, H., "CGE: automatic generation of controllers in the CATHEDRAL-II silicon compiler," Proceedings of the European Design Automation Conference (EDAC), pp. 617-621, March 1990.
J. Rabaey and M. Potkonjak, "Resource Driven Synthesis in the HYPER System", Proceedings ISCAS 1990, New Orleans, May 1990.
D. Genin, J. Rabaey, P. Hilfinger, C. Scheers and H. De Man, "DSP Specification using the SILAGE Language", Proceedings IEEE ICASSP Conference, Albequerque, April 1990.
D. Chen, R. Yu, J. Rabaey and R. Brodersen, "A VLSI Grammar Processing SubSystem for a Real Time Large Vocabulary Continuous Speech Recognition System", Proceedings IEEE CICC 1990 Conf., Boston, May 1990.
M. Potkonjak and J. Rabaey, "Retiming for Scheduling", Proc. IEEE Workshop on VLSI Signal Processing, pp. 23-32, November 1990.
D. Chen and J. Rabaey, "PADDI : Programmable Arithmetic Devices for Digital Signal Processing", Proc. IEEE Workshop on VLSI Signal Processing, pp. 240-249, November 1990.
P. Hoang and J. Rabaey, "Program Partitioning for a Reconfigurable MultiProcessor System", Proc. IEEE Workshop on VLSI Signal Processing, pp.53-62, November 1990.
A. Stolzle, S. Narayanaswamy, P. Schrupp, B. Richards, R. Yu. J. Rabaey and R. Brodersen, "A Flexible VLSI 60,000 Word Real Time Continuous Speech Recognition System", Proc. IEEE Workshop on VLSI Signal Processing, pp. 247-284, November 1990.
A. Kapadia, J. Rabaey and D. Backer, "A Finite Impulse Response Integrated Circuit for Pulsar Recovery", Proceedings IEEE AP and ARS combined Conference, June 1991.
J. Rabaey and M. Potkonjak, "Estimation in High Level Synthesis", IFIP International Workshop on Application of Synthesis and Simulation, Lenggries, August 1991.
J. Rabaey and M. Potkonjak, "Complexity Estimation for Real Time Application Specific Circuits", Proc. IEEE ESSCIRC Conference, Milan, September 1991.
M. Potkonjak and J. Rabaey, "Optimizing the Resource Utilization Using Transformations", Proc. IEEE ICCAD Conference, November 1991.
P. Landman and J. Rabaey, "Design for Low Power with Applications to Speech Coding", Proc. International Micro-Electronics Conference, Cairo, December 1991.
D. Chen and J. Rabaey, "A Reconfigurable Multiprocessor IC for Rapid Prototyping of Real Time Data Paths", Proc. IEEE ISSCC Conference, pp. 74-75, San Francisco, February 1992.
D. Chen, L. Guerra, E. Ng, D. Schultz, C. Yu and J. Rabaey, "A Field Programmable Architecture for High Speed Signal Processing Applications", Proc. 1992 ACM Workshop on Field Programmable Gate Arrays, pp. 117-122, Berkeley, February 1992.
C. Chu and J. Rabaey, "Hardware Selection and Clustering in the HYPER Synthesis System", Proceedings EDAC Conference, Brussels, March 1992.
P. Hoang and J. Rabaey, "A Compiler for MultiProcessor DSP Implementation", Proceedings ICASSP Conference, pp. 581-584, San Francisco, March 1992.
M. Potkonjak and J. Rabaey, "Fast Implementation of Recursive Programs Using Transformations", Proceedings ICASSP Conference, San Francisco, pp. V569-572, March 1992.
M. Potkonjak and J. Rabaey, "Probabilistic Rejectionless Anti-Voter Optimization Algorithm", Proceedings ISCAS Conference, San Diego, May 1992.
P. Hoang and J. Rabaey, "Hierarchical Scheduling of DSP Programs onto MultiProcessors for Maximum Throughput", Proc. ASAP92 International Conference on Application Specific Array Processors , Berkeley, August 1992.
M. Potkonjak and J. Rabaey, "Pipelining: Just Another Transformation", Proc. ASAP92 International Conference on Application Specific Array Processors, Berkeley, August 1992.
D. Chen, L. Guera, E. Ng, M. Potkonjak, D. Schultz and J. Rabaey, "An Integrated System for Rapid Prototyping of High Speed, Algorithmic Specific Data Paths", Proc. ASAP92 International Conference on Application Specific Array Processors, Berkeley, August 1992.
A. Yeung and J. Rabaey, "A Data-Driven Architecture for Rapid Prototyping of High Throughput DSP Algorithms", Proceedings VLSI Signal Processing Workshop, IEEE Press, pp. 225-234, Napa, October 1992.
A. Chandrakasan, M. Potkonjak, J. Rabaey and R. Brodersen, "An Approach for Power Minimization using Transformations", VLSI Signal Processing Workshop, IEEE Press, pp. 41-50, Napa, October 1992.
M. Potkonjak and J. Rabaey, "Maximally Fast and Arbitrarily Fast Implementation of Linear Computations", IEEE ICCAD Conf, Santa Clara, November 1992.
A. Chandrakasan, M. Potkonjak, J. Rabaey and R. Brodersen, "Hyper-LP: A System for Power Minimization Using Architectural Transformations," IEEE ICCAD Conf, Santa Clara, November 1992.
A. Yeung and J. Rabaey, "A Reconfigurable Data Driven Multi-Processor Architecture for Rapid Prototyping of High Throughput DSP Algorithms", Proceedings HICCS Conference, Hawaii, January 1993.
P. Landman and J. Rabaey, "Power Estimation for High Level Synthesis" Proceedings EDAC Conference, Paris, February 1993.
M. Potkonjak and J. Rabaey, "DSP Arithmetic Computation has Unlimited Parallellism", Proceedings ICASSP Conference, Minneapolis, April 1993.
S. Huang and J. Rabaey, "Behavioral Transformations to Maximize the Throughput of Real Time Applications", SRC Techcon, Atlanta, September 1993.
S. Lee and J. Rabaey, "A Hardware-Software Co-simulation Environment", Proceedings Hardware-Software Co-design Workshop, Cambridge, October 1993.
Jan M. Rabaey, "Fast Prototyping of Real Time Systems: A New Challenge?", Proceedings of the 1993 IEEE Workshop on VLSI Signal Processing, October 20-22, 1993, Koningshof, Veldhoven, The Netherlands (invited paper).
M. Potkonjak and J. Rabaey, "Exploring the Algorithmic Design Space using High Level Synthesis", Proceedings of the 1993 IEEE Workshop on VLSI Signal Processing, October 20-22, 1993, Koningshof, Veldhoven, The Netherlands.
L. Guerra, M. Potkonjak, and J. Rabaey, "High Level Synthesis for Efficient Built-in Self Repair", 1993 International Workshop on Defect and Fault Tolerance in VLSI Systems, Venice, October 1993.
M. Potkonjak, L. Guerra and J. Rabaey, "Heterogenous BISR Techniques for Yield and Reliability Enhancement using High Level Synthesis Transformations", 1993 International Conference on Application Specific Array Processors, Venice, October 1993.
M. Corazao, M. Khalaf, L. Guerra, M. Potkonjak and J. Rabaey,"Instruction Set Mapping for Performance Optimization", Proceedings IEEE ICCAD Conference, November 1993.
L. Guerra, M. Potkonjak and J. Rabaey, "High Level Synthesis for Reconfigurable Data Path Structures", Proceedings IEEE ICCAD Conference, November 1993.
J. Rabaey and L. Guerra, "Exploring the Architectural and Algorithmic Design Space of Real Time Applications", Proceedings ICVC 93, pp. 315-319, Taejon, Korea, November 1993 (invited paper).
S. Huang and J. Rabaey, "Behavioral Transformations to maximize the throughput of real time applications", Proceedings of EDAC-EUROASIC 1994, pp. 25-30, Paris, Febr. 1994.
P. Landman, J. Rabaey, "Black-Box Capacitance Models for Architectural Power Analysis," Proceedings 1994 International Workshop on Low Power Design, Napa, CA, April 24-27, 1994, pp. 165-170.
R. Mehra, J. Rabaey, "Behavioral Level Power Estimation and Exploration," Proceedings 1994 International Workshop on Low Power Design, Napa, CA, April 24-27, 1994, pp. 197-202.
I. Verbauwhede, C. Scheers, J. Rabaey, "Specification and Support of Multi-Dimensional DSP in the Silage Language," Proceedings of ICASSP-94, Sydney, Australia, April, 1994.
L. Guerra, M. Potkonjak, J. Rabaey, "Concurrency Characteristics in DSP Programs," Proceedings ICASSP-94, Sydney, Australia, April, 1994.
I. Verbauwhede, C. Scheers, J. Rabaey, "Memory Estimation for High Level Synthesis," Proceedings Design Automation Conference, San Diego, CA, June, 1994.
D. Lidsky, J. Rabaey, "Low-Power Design of Memory Intensive Functions Case Study: Vector Quantization," Proceedings 1994 IEEE Workshop on VLSI Signal Processing, La Jolla, CA, Oct. 26-28, 1994.
L. Guerra, M. Potkonjak, J. Rabaey, "System-Level Design Guidance Using Algorithm Properties," Proceedings 1994 IEEE Workshop on VLSI Signal Processing, La Jolla, CA, Oct. 26-28, 1994
M. Potkonjak, J. Rabaey, "Area-Time VLSI High Level Synthesis: Theory and Practice," Proceedings 1994 IEEE Workshop on VLSI Signal Processing, La Jolla, CA, Oct. 26-28, 1994.
D. Lidsky and J. Rabaey, "Low Power Design of Memory Intensive Functions", Proceedings 1994 Symposium on Low Power Electronics, San Diego, Oct. 1994.
M. Le, S. Seshan, F. Burghardt, and J. Rabaey, "Software Architecture for the Infopad System," Proceedings of the Mobidata Workshop, Rutgers University, New Jersey, October, 1994.
M. Potkonjak and J. Rabaey, "Algorithm Selection: A Quantitative Computation-Intensive Optimization Approach", Proc. ICCAD Conference, Santa Clara, Nov. 1994.
B. Brodersen et al, "Research Challenges in Wireless Multimedia," IEEE Perosnal, Indoor and Mobile Radio Communications (PIMRC) Workshop, pp. 1- 5, Sept. 1994.
A. Yeung, and J. Rabaey, "A 2.4 GOPS Data-Driven Reconfigurable Multiprocessor IC for DSP," Proceedings of the IEEE International Solid-State Circuits Conference, San Francisco, CA, February 1995.
A. Yeung, and J. Rabaey, "A 210 Mb/s Radix-4 Bit-level Pipelined Viterbi Decoder," Proceedings of the IEEE International Solid-State Circuits Conference, pp. 169-176, San Francisco, CA, February 1995.
M. Le, F. Burghardt, S. Seshan, and J. Rabaey, "InfoNet: The Networking Infrastructure of Infopad," Proceedings of the IEEE COMPCON '95, pp. 163-168, San Francisco, CA, March, 1995.
E. Brewer et al., "Design of wireless portable systems," Proceedings of the IEEE COMPCON '95, pp. 163-168, San Francisco, CA, March, 1995.
F. Burghardt, M. Le, S. Seshan and J. Rabaey, "Software Architecture of the INFOPAD", ICC Conference, 1995.
P. Landman and J. Rabaey, "Activity-Sensitive Architectural Power Analysis for the Control Path," Proceedings of the 1995 International Symposium on Low-Power Design, pp. 93-98, Dana Point, CA, April, 1995.
M. Potkonjak and J. Rabaey, "Power Minimization in DSP Application-Specific Systems using Algorithm Selection," in Proc. 1995 IEEE ICCASSP Conference, pp. 2639-2642, Detroit, May 1995.
J. Rabaey, M. Potkonjak and K. Wakabayashi, "Efficient throughput optimization of feedback linear computations using Generalized Horner's scheme," in Proc. 1995 IEEE ICCASSP Conference, pp. 2659-2662, Detroit, May 1995.
J. Rabaey, L. Guerra, and R. Mehru, "Design Guidance in the Power Dimension", in Proc. 1995 IEEE ICASSP Conference, pp. 2837-2840, Detroit, May 1995.
O. Bentz, D. Lidsky, J. Rabaey, "Information Based Design Environment," Proceedings of the IEEE VLSI Signal Processing Workshop, Osaka, October, 1995, also in VLSI Signal Processing VIII, IEEE Press, pp.237-246, Oct. 1995.
R. Mehra , L. Guerra, J. Rabaey, "Exploiting Locality for Low-Power Design," Proceedings of the Custom Integrated Circuit Conference, pp. 401-404, May 1996.
J. Rabaey, "Exploring the Low-power Dimension", Proceedings of the Custom Integrated Circuit Conference, pp. 215-220, May 1996.
D. Lidsky and J. Rabaey, "Early Power Estimation - A Worldwide Web Application", Proceedings 33rd Design Automation Conference, pp. 27-32, Las Vegas, June 1996.
Le, M.T.; Rabaey, J., "A global QoS management for wireless networks", Proceedings of 1996 IFIP World Conference on Mobile Communications, Canberra, Australia, pp. 205-218, Sept. 1996.
L. Guerra, M. Potkonjak, J. Rabaey "Divide-and-conquer techniques for global throughput optimization", Proceedings of the IEEE VLSI Signal Processing Workshop, San Francisco, pp. 137-46, October 1996.
Shan-Hsi Huang; Rabaey, J.M, " An integrated framework for optimizing transformations", Proceedings of the IEEE VLSI Signal Processing Workshop, San Francisco, pp. 263-72, October 1996.
Arthur Abnous and Jan Rabaey, "Ultra-Low-Power Domain-Specific Multimedia Processors," Proceedings of the IEEE VLSI Signal Processing Workshop, San Francisco, pp. 461-470, October 1996.
Mehra, R.; Rabaey, J., "Exploiting regularity for low-power design", Transactions IEEE ICCAD Conference, San Jose, pp. 166-172, Nov. 1996.
J. Rabaey, "Reconfigurable Processing: The Solution to Low-Power Programmable DSP", Proceedings ICASSP 1997, Munich, pp. , April 1997.
Ole Bentz, David B. Lidsky, Jan Rabaey, "A Dynamic Design Estimation and Exploration Environment", Proceedings of the IEEE/ACM Design Automation Conference, pp. 190-195, June 1997.
V. Srini, N. Chow, R. Sutton, J. Rabaey, "MultiPADDI-2 board for image processing," Proceedings of the SPIE - The International Society for Optical Engineering, vol.3166: pp. 78-89, August 1997.
V. Srini, J. Rabaey, "An architecture for web-based image processing," Proceedings of the SPIE - The International Society for Optical Engineering, vol.3166, pp. 90-101, August 1997.
J. Rabaey, "System-Level Power Estimation and Optimization - Challenges and Perspectives", International Symposium on Low-Power Design, pp. 158-160, Monterey, August 1997.
J. Rabaey, A. Abnous, Y. Ichikawa, K. Seno and M. Wan., "Heterogeneous Reconfigurable Systems", Proc. 1997 IEEE Workshop on Design and Implementation of Signal Processing Systems, Leicester, England, pp. 24-34, November 1997.
J. Rabaey et al., "Hybrid reconfigurable processors-the road to low-power consumption", IEEE VLSI Conference, pp. 300-303, Madras, India, January 1998.
Rabaey, J.; Wan, M. "An energy-conscious exploration methodology for reconfigurable DSPs", Proceedings. Design, Automation and Test in Europe (DATE) Conference, pp. 341-342, Paris, February 1998.
Abnous, A.; Seno, K.; Ichikawa, Y.; Wan, M.; Rabaey, J. (Edited by Rolim, J.), "Evaluation of a low-power reconfigurable DSP architecture", Proc. Parallel and Distributed Processing. SPDP '98 Workshops, p.55-60, Springer-Verlag, March 1998
Rabaey, J.M. (Edited by: Smailagic, A.; Brodersen, R.De Man, H.), "Experiences and challenges in system design", Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design, pp. 2-4, Orlando, Florida, April 1998.
Wan, M.; Ichikawa, Y.; Lidsky, D.; Rabaey, J., "An energy conscious methodology for early design exploration of heterogeneous DSPs", Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, p.111-117, Santa Clara, May 1998.
Roy A. Sutton, Vason P. Srini, Jan M. Rabaey, "A Multiprocessor DSP Systems Using PADDI-2," Proceedings of the 35th IEEE/ACM Design Automation Conference, pp. 62-65, June 1998.
Guerra, L.; Potkonjak, M.; Rabaey, J, "A methodology for guided behavioral-level optimization", Proceedings 35th Design and Automation Conference, p.309-14, June 1998.
Srini, V.P.; Thendean, J.; Ueng, S.-Z.; Rabaey, J.M. "Parallel DSP with memory and I/O processors. Proceedings of the SPIE - The International Society for Optical Engineering, vol.3452, pp 2-13, (Parallel and Distributed Methods for Image Processing II, San Diego, CA, USA, 19-20 July 1998.
Hui Zhang, Jan Rabaey, "Low-Swing Interconnect Interface Circuits," Proceedings of International Symposium on Low Power Electronics and Design, pp 161-166, Monterey, CA, August 1998.
Kusse, E.; Rabaey, J., "Low-energy embedded FPGA structures", Proceedings 1998 International Symposium on Low Power Electronics and Design, pp 155-160, Monterey, CA, August 1998.
J . Rabaey, "Design Methodology and Tools for Wireless System Design", Proceedings 1998 Norchip Conference, pp. 183-189, Lund, Sweden, November 1998.
Zhang, Hui, Marlene Wan, Varghese George, Jan Rabaey, "Interconnect Architecture Exploration for Low Energy Reconfigurable Single-Chip DSPs" Proceedings of the WVLSI , Orlando, FL, USA, April 1999.
V. George, H. Zhang, and J. Rabaey,
“The Design of
a Low Energy FPGA,” Proceedings 1999 International Symposium on Low
Suet-Fei Li; Wan, M.; Rabaey, J., “Configuration code generation and optimizations for heterogeneous reconfigurable DSPs, “ Proceedings 1999 IEEE Workshop on Signal Processing Systems. SiPS 99, Taipei. Taiwan, October 1999, pp. 168-180.
Wan, M.; Hui Zhang; Benes, M.; Rabaey, J., “A low-power reconfigurable data-flow driven DSP system,” Proceedings 1999 IEEE Workshop on Signal Processing Systems. SiPS 99, Taipei. Taiwan, October 1999, pp. 191-200.
Rabaey, J., “Low-power silicon architectures for wireless communications”, Proceedings ASP-DAC 2000, Yokohama, Japan, Jan. 2000, pp. 377-380.
Ghazal, N.; Newton, R.; Rabaey, J., “Retargetable estimation scheme for DSP architecture selection,” Proceedings ASP-DAC 2000, Yokohama, Japan, Jan. 2000, pp. 377-380.
H. Zhang, V.
Prabhu, V. George, M. Wan, M. Benes, A. Abnous, and J. Rabaey,
“A 1 V
Heterogeneous
J.
Rabaey, J. Ammer, J.L. da Silva Jr., D. Patel,
“PicoRadio: Ad-hoc Wireless
Networking of Ubiquitous Low-
Da Silva, J.L., Jr.; Sgroi, M.; De Bernardinis, F.; Li, S.F.; Sangiovanni-Vincentelli, A.; Rabaey, J., “Wireless protocols design: challenges and opportunities,” Proceedings of the Eighth International Workshop on Hardware/Software Codesign CODES 2000, San Diego, May 2000, pp. 147-151.
Sgroi M, da Silva JL Jr, De Bernardinis F, Burghardt F, Sangiovanni-Vincentelli A, Rabaey J., "Designing wireless protocols: methodology and applications," Proceedings 2000 IEEE International Conference on Acoustics, Speech, and Signal Processing, June 2000, pp.3726-9 vol.6.
Ghazal, N.; Newton, R.; Rabaey, J., “Predicting Performance Potential of Modern DSPs,” Proceedings Design Automation Conference 2000, Los Angeles, June 2000, pp. 332-336.
J. Musicer and J. Rabaey, “An Analysis of MOS Current Mode Logic for Low Power and High Performance Digital Logic,” Proceedings ISLPED 2000, July 2000.
Rabaey JM,
“Silicon Platforms for the Next Generation Wireless Systems – What Role
does Reconfigurable Hardware Play?” Field-Programmable
Logic and Applications. 10th International Conference, FPL 2000, Austria,
Proceedings Springer-Verlag. 2000, pp.277-85.
Koushanfar F, Prabhu V, Potkonjak M, Rabaey JM., "Processors for mobile applications," Proceedings 2000 International Conference on Computer Design (ICCD00), Sept.. 2000, pp.603-8.
Rabaey JM, Potkonjak M, Koushanfar F, Suet-Fei Li, Tuan T., "Challenges and opportunities in broadband and wireless communication designs, Proceedings IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000, Nov. 2000, pp.76-82 .
da Silva JL Jr, Shamberger J, Ammer MJ, Guo C, Li S,
Shah R, Tuan T, Sheets M, Rabaey JM, Nikolic B,
Sangiovanni-Vincentelli A, Wright P. "Design
methodology for PicoRadio networks," Proceedings Design,
Automation and Test in
Tim Tuan, Suet-Fei Li, Rabaey J. Reconfigurable platform design for wireless protocol processors. Proceedings 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings Part vol.2, May 2001, pp.893-6.
Savarese C, Rabaey JM, Beutel J. Locationing in distributed ad-hoc wireless sensor networks. 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings, May 2001, Part vol.4, pp.2037-40.
Lizhi Charlie Zhong, Rahul Shah, Chunlong Guo, Jan Rabaey, "An Ultra-Low Power and Distributed Access Protocol for Broadband Wireless Sensor Networks," IEEE Broadband Wireless Summit, Las Vegas, N.V., May 2001.
Sgroi M, Sheets M, Mihal A, Keutzer K, Malik S, Rabaey J, Sangiovanni-Vincentelli A. "Addressing the system-on-a-chip interconnect woes through communication-based design." Proceedings of the 38th Design Automation Conference, Las Vegas, June 2001, pp.667-72.
Suet-Fei Li, Roy Sutton, Jan Rabaey, "Low Power Operating System for Heterogeneous Wireless Communication Systems," PACT 01 Conference, Barcelona, Spain September 8-12, 2001.
Chunlong Guo, Lizhi Charlie Zhong, Rabaey JM., "Low power distributed MAC for ad hoc sensor radio networks," GLOBECOM'01, IEEE Global Telecommunications Conference, San Antonio, November 2001, Part vol 5, pp.2944-8
Zhong LC, Rabaey J, Chunlong Guo, Shah R. Data link layer design for wireless sensor networks. Proceedings IEEE 2001 MILCOM Conference, Oct. 2001, pp.352-6 .
Rabaey JM, Ammer J, Karalar T, Suetfei Li, Otis B, Sheets M, Tuan T. "PicoRadios for wireless sensor networks: the next challenge in ultra-low power design., 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers , February 2002, San Francisco, pp.200-1.
Shah RC, Rabaey JM. Energy aware routing for low energy ad hoc sensor networks. 2002 IEEE Wireless Communications and Networking Conference Record. WCNC 2002, Orlando, Florida, March 2002, pp.350-5 .
Rabaey JM and Sangiovanni-Vincentelli A., "System-on-a-Chip - A Platform Perspective", Proceedings 9th Korean Conference on Semiconductors, April 2002.
Willig A, Shah R, Rabaey J, Wolisz A. Altruists in the PicoRadio sensor network. Proceedings 4th IEEE International Workshop on Factory Communication Systems (WFCS), Varsalas Sweden, August 2002, pp.175-84 .
Rabaey J., "Ultra low-energy transceivers for wireless sensor networks," Proceedings 15th Symposium on Integrated Circuits and Systems Design, Porto Allegre, Brazil, September 2002, pp.386.
Savarese C, Langendoen K. and Rabaey J, Robust positioning algorithms for distributed ad-hoc wireless sensor networks. Proceedings of the 2002 USENIX Annual Technical Conference, Monterey, June 2002, pp.317-27.
Otis BP, Rabaey JM. A 300 mu W 1.9GHz CMOS oscillator utilizing micromachined resonators. ESSCIRC 2002, Proceedings of the 28th European Solid-State Circuit Conference, Florence, September 2002, pp.151-4.
Rong Chen, Marco Sgroi, Grant Martin, Luciano Lavagno, Alberto Sangiovanni-Vincentelli, Jan Rabaey, Embedded System Design Using UML and Platforms, Proceedings of Forum on Specification and Design Languages 2002 (FDL'02), September, 2002.
Martin Kubisch, Holger Karl, Adam Wolisz, Lizhi Charlie Zhong, Jan Rabaey, "Distributed Algorithms for Transmission Power Control in Wireless Sensor Networks," Proceedings WCNS03, IEEE Wireless Communications and Networking Conference, New Orleans, March 2003.
Konstantinos Sarrigeorgidis, Jan M. Rabaey, "Massively Parallel Wireless Reconfigurable Processor Architecture and Programming", 10th Reconfigurable Architectures Workshop RAW 2003, April 22, 2003, Nice, France.
Jan M. Rabaey, "Ultra-Low Cost and Power Communication and Computation Enables Ambient Intelligence," Proceedings Smart Object Conference, Grenoble, May 03, pp 11-13.
Dragan Petrovic , Rahul C. Shah, Kannan Ramchandran, Jan Rabaey, "Data Funneling: Routing with Aggregation and Compression for Wireless Sensor Networks," SNPA Workshop, ICC 2003 International Conference on Communications, Anchorage, May 2003.
M. Josie Ammer, Michael Sheets, Tufan Karalar, Mika Kuulusa, and Jan Rabaey, "A Low-Energy Chip-Set for Wireless Intercom," Proceedings 40th Design Automation Conference, Anaheim, June 2003, pp. 916-919.
J. van Greunen, J. Rabaey, "Lightweight Time Synchronization for Sensor Networks," Proceedings WSNA 2003, San Diego, CA September 2003.
S. Roundy, B. Otis, Y.H. Chee, J. Rabaey, P. Wright, "A 1.9GHz RF Transmit Beacon using Environmentally Scavenged Energy," Digest IEEE Int.Symposium on Low Power Elec. and Devices, Seoul, Korea, Sept. 2003.
Yu Cao; Huifang Qin; Wang, R.; Friedberg, P.; Vladimirescu, A.; Rabaey, J.; "Yield optimization with energy-delay constraints in low-power digital circuits," 2003 IEEE Conference on Electron Devices and Solid-State Circuits, pp. 285 - 288 , Dec. 2003.
Huifang Qin; Yu Cao; Markovic, D.; Vladimirescu, A.; Rabaey, J., "SRAM leakage suppression by minimizing standby supply voltage," Proceedings. 5th International Symposium on Quality Electronic Design, 2004, April 2004.
Chee, Y.H.; Rabaey, J.; Niknejad, A.M., "A class A/B low power amplifier for wireless sensor networks," ISCAS '04. Proceedings of the 2004 International Symposium on Circuits and Systems, Volume: 4, pp. IV - 409-12 Vol.4, May 2004.
Otis, B.P.; Chee, Y.H.; Lu, R.; Pletcher, N.M.; Rabaey, J.M., "An ultra-low power MEMS-based two-channel transceiver for wireless sensor networks," Digest of Technical Papers. 2004 Symposium on VLSI Circuits, 2004, pp. 20 - 23, 17-19 June 2004.
Lin, E.A., Rabaey, J.M. Wolisz, A., "Power-efficient rendez-vous schemes for dense wireless sensor networks," 2004 IEEE International Conference on Communications, Volume 7, pp. 3769 - 3776, Paris, June 2004.
Van Greunen, J.; Petrovi, D.; Bonivento, A.; Jan Rabaey; Ramchandran, K.; Sangiovanni-Vincentelli, A., "Adaptive sleep discipline for energy conservation and robustness in dense sensor networks," 2004 IEEE International Conference on Communications, Volume 6, pp. 3657 - 3662, Paris, June 2004.
Zhong, L.C.; Rabaey, J.M.; Wolisz, A., "An integrated data-link energy model for wireless sensor networks," 2004 IEEE International Conference on Communications, Volume 7, pp. 3777 - 3783 , Paris, June 2004.
Vladimirescu, A.; Yu Cao; Thomas, O.; Huifang Qin; Markovic, D.; Valentian, A.; Ionita, R.; Rabaey, J.; Amara, A., "Ultra-low-voltage robust design issues in deep-submicron CMOS," The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, NEWCAS 2004, pp.49-52, Montreal, June 2004.
Karalar, T.C.; Yamashita, S.; Sheets, M.; Rabaey, J., "An integrated, low power localization system for sensor networks," Mobiquitous 2004, The First Annual International Conference on Mobile and Ubiquitous Systems: Networking and Services, pp. 24-30, Aug. 22-26, 2004.
Ammer, M.J.; Rabaey, J., "Frequency offset estimation with improved convergence time and energy consumption," 2004 IEEE Eighth International Symposium on Spread Spectrum Techniques and Applications, pp. 596-600, Sept. 2004.
Karalar, T.C.; Yamashita, S.; Sheets, M.; Rabaey, J., "A low power localization architecture and system for wireless sensor networks," IEEE Workshop on Signal Processing Systems, SIPS 2004., pp. 89-94, Oct. 2004.
Shah, R.C.; Bonivento, A.; Petrovic, D.; Lin, E.; van Greunen, J.; Rabaey, J., "Joint optimization of a protocol stack for sensor networks," IEEE Military Communications Conference MILCOM 2004. Volume 1, 31, pp 480-486, Nov. 2004.
Rabaey, J.M., "Design at the end of the silicon roadmap," Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), 2005, Volume 1, 18-21, Shanghai, Jan. 2005.
Otis, B.; Chee, Y.H.; Rabaey, J, "A 400 uW-RX, 1.6mW-TX superregenerative transceiver for wireless sensor networks," Digest of Technical Papers, IEEE International Solid-State Circuits Conference, 2005, pp. 396 - 398, Febr. 2005.
P. Friedberg, Y. Cao, J. Cain, R. Wang, J.M. Rabaey, and C. Spanos, “Modeling within-field gate length spatial variation for process-design co-optimization,” Proceedings of SPIE – Int. Soc. Opt. Eng., pp. 178-188, Febr. 2005.
Zhong, L.C.; Rabaey, J.M.; Wolisz, A., "Does proper coding make single hop wireless sensor networks reality: the power consumption perspective," IEEE Wireless Communications and Networking Conference, WCNC 2005, Volume 2, pp. 664-669, March 2005.
Ammer, J.; Rabaey, J., "Low power synchronization for wireless sensor network modems," IEEE Wireless Communications and Networking Conference, WCNC 2005, Volume 2, pp670-675, March 2005.
Shah, R.C.; Wietholter, S.; Wolisz, A.; Rabaey, J.M., "When does opportunistic routing make sense?," Third IEEE International Conference on Pervasive Computing and Communications, PerCom 2005 Workshops. T 8-12, pp 350-356, March 2005.
Friedberg, P.; Cao, Y.; Cain, J.; Wang, R.; Rabaey, J.; Spanos, C., "Modeling within-die spatial correlation effects for process-design co-optimization," Sixth International Symposium on Quality of Electronic Design, ISQED 2005, pp. 516-521, March 2005.
Shah, R.C.; Wolisz, A.; Rabaey, J.M., "On the performance of geographical routing in the presence of localization errors," IEEE International Conference on Communications, ICC 2005, Volume 5, pp. 2979 - 2985, May 2005.
Chee, Y.H.; Niknejad, A.M.; Rabaey, J., "A sub-100 uW 1.9-GHz CMOS oscillator using FBAR resonator," Digest of Papers. IEEE Radio Frequency integrated Circuits (RFIC) Symposium, 2005, pp. 123-126, June 2005.
Petrovic, D.; Ramchandran, K.; Rabaey, J., "Coding for sensor networks using untuned radios ," IEEE 6th Workshop on Signal Processing Advances in Wireless Communications, pp. 1093-1097, June 2005.
Josephine Ammer and Jan Rabaey, "The Energy-per-Useful-Bit Metric for Evaluating and Optimizing Sensor Network Physical Layers," Proceedings of the IEEE International Workshop on Wireless Ad Hoc & Sensor Networks, June 2005.
F. Bacchini, J.M. Rabaey, A. Cox, F. Lane, R. Lauwereins, U. Ramacher, and D. Witt, “Wireless platforms: GOPS for cents and MilliWatts,” Proceedings of the 42nd Design Automation Conference, pp. 351-352, June 2005.
Chee, Y.H.; Niknejad, A.M.; Rabaey, J. "An ultra-low power injection locked transmitter for wireless sensor networks," Proceeding of the IEEE Custom Integrated Circuits Conference, 2005, 18-21 Sept. 2005 Page(s):797 - 800.
Li, Y.; De Bernardinis, F.; Otis, B.; Rabaey, J.M.; Vincentelli, A.S., "Low-power mixed-signal baseband system design for wireless sensor networks," Proceedings of the IEEE Custom Integrated Circuits Conference, 18-21 Sept. 2005 Page(s):55 - 58
Pletcher, N.M.; Rabaey, J.M., "A 100 /spl mu/W, 1.9GHz oscillator with fully digital frequency tuning," Proceedings of the 31st European Solid-State Circuits Conference, ESSCIRC 2005, 2-16 Sept. 2005 Page(s):387 - 390
Petrovic, D.; Ramchandran, K.; Rabaey, J., "Throughput of wireless networks of untuned radios," 7th International Conference on Telecommunications in Modern Satellite, Cable and Broadcasting Services, 2005. , Volume 2, 28-30 Sept. 2005, Page(s):339 - 343 vol. 2.
Lin, E.-Y.A.; Rabaey, J.M.; Wiethoelter, S.; Wolisz, A., "Receiver initiated rendezvous schemes for sensor networks," Global Telecommunications Conference, 2005. GLOBECOM '05. IEEE Volume 5, 28 Nov.-2 Dec. 2005 Page(s):6 pp.
Marculescu, R.; Rabaey, J.; Sangiovanni-Vincentelli, A. "Is “Network” the Next “Big Idea” in Design?," Design, Automation and Test in Europe, 2006. DATE '06. Proceedings, Volume 1, 06-10 March 2006 Page(s):1 - 3.
Karalar, T.C.; Rabaey, J., "An RF ToF Based Ranging Implementation for Sensor Networks," 2006 IEEE International Conference on Communications, Volume 7, June 2006, Page(s):3347 - 3352
Sheets, M.; Burghardt, F.; Karalar, T.; Ammer, J.; Chee, Y.; Rabaey, J, "A Power-Managed Protocol Processor for Wireless Sensor Networks," Digest of Technical Papers 2006 Symposium on VLSI Circuits, June 15-17, 2006, Page(s):212 - 213.
Chee, Y; Niknejad, A; Rabaey, J.; "A 46% Efficient 0.8dBm Transmitter for Wireless Sensor Networks," Digest of Technical Papers 2006 Symposium on VLSI Circuits, June 15-17, 2006, Page(s):43 - 44.
Chris R. Baker, Yury Markovsky, Jana Van Gruenen, Adam Wolisz, Jan Rabaey, and John Wawrzynek, "ZUMA: A Platform for Smart-Home Environments", In Proceedings of IET Intelligent Environments. Athens, Greece. July, 2006.
Jana Van Gruenen, Yury Markovsky, Chris R. Baker, Adam Wolisz, Jan Rabaey, and John Wawrzynek. "ZUMA: A Platform for Smart-Home Environments, The Case for Infrastructure." In Proceedings of IET Intelligent Environments. Athens, Greece. July, 2006.
J. Rabaey, "Analysis of non-ideal s.c.-circuits including resistances and opamp poles", Proceedings of the S2C3 Summercourse, Katholieke Universiteit Leuven, June 1981.
J. Rabaey, "A Unified Computer Aided Design Technique for Switched Capacitor Systems in the Time and the Frequency Domain," PhD Thesis, Katholieke Universiteit Leuven, Belgium, April 1983.
H. De Man, J. Rabaey, P. Six, L. Claesen : "ESPRIT 97 : Towards a Silicon Compilation System for VLSI Digital Signal Processing", ESPRIT Technical Week, Brussels, September 28 - October 1,1986.
J. Rabaey, "Silicon Compilation and Design Synthesis", Proceedings 1988 CERN School Of Computing, Oxford, August 1988.
R. Brodersen and J.Rabaey, "Evolution of VLSI Signal Processing Circuits", Proceedings Workshop on Accoustics and Audio, 1989.
J. Rabaey, "Low Power Digital Design," Proceedings Custom Integrated Circuits Conference, San Diego, CA, May 1-4, 1994.
S. Huang, J. Rabaey, "TAO: A Transformation Framework for DSP Algorithm Optimization," ERL/UCB Memorandum, August 1, 1995.
J. Rabaey, E. Arens, C. Federspiel, A. Gadgil , D. Messerschmitt, W. Nazaroff, K. Pister, S. Oren, P. Varaiya, "Smart Energy Distribution and Consumption: Information Technology as an Enabling Force," White Paper, Center for Information Technology Research in the Interest of Society (CITRIS), 2001.
Jan M. Rabaey, Sharad Malik, Gary Baldwin and the GSRC Executive Committee, "White paper on Future Directions in GSRC - A proposal for collaborative research in the design, verification, and test of integrated gigascale systems," white paper, November 2002.
M. Sgroi, A. Wolisz, A. Sangiovanni-Vincentelli and J. Rabaey, "A Service-Based Universal Application Interface for Ad-hoc Wireless Sensor Networks," white paper, December 2003.
US Patent No. 5,502,645, "Behavioral Synthesis for Reconfigurable Datapath Structures", (with L. Guerra and M. Potkonjak).