A Power/Area Optimal VLSI Signal Processing  (Abstract)

Dejan Markovic

(Professors Robert W. Brodersen and Borivoje Nikolic)

The complexity of integrated circuits found in wireless communication devices has been steadily increasing to support more functionality and new ideas from communication theory.  A recent example of MIMO communication suggests the use of multi-dimensional signal processing algorithms which require us to rethink the way we approach hardware implementation in terms of power and area.

We present a hierarchical methodology for rapid hardware realization of very complex signal processing algorithms that optimizes the architecture for reduced power and area, taking into account unique features of scaled technology such as leakage power and process variation.  We start from algorithm description in widely adopted graphical Simulink environment and turn this model into an ASIC chip in a highly automated fashion.  Optimal architecture balances the algorithm throughput requirement with the energy-performance capability of the underlying circuits, [1].  This is demonstrated on a wideband 4x4 MIMO channel decoupling through singular value decomposition, [2].  A complexity of 170 G additions/sec can be realized in 3.5mm² of silicon area with an energy-efficiency of 5 GOPS/mW in a 90nm CMOS technology.  Looking forward, it is interesting to consider the cost of adding flexibility required for multi-standard operation.

References:

[1]  D. Markovic, V. Stojanovic, B. Nikolic, M.A. Horowitz, and R.W. Brodersen, "Methods for True Energy-Performance Optimization," IEEE J. Solid-State Circuits, vol. 39, no. 8, pp. 1282-1293, Aug. 2004.

[2]  Ada S. Y. Poon, David N. C. Tse, and Robert W. Brodersen, “An adaptive multiple-antenna transceiver for slowly flat-fading channels,” IEEE Trans. on Communications, vol. 51, pp. 1820-1827, November 2003.