Welcome
to the homepage of Huifang Qin. I'm currently a 6th year Ph.D student
in professor Jan. M.
Rabaey's group at the University of
California, Berkeley. My dissertation research focus on robust and ultra-low
power VLSI design. The goal is to develop circuit and architecture level
techniques, as well as design strategies to achieve ultra-low power consumption
and robust functionality for computing and communication systems. My research
interests range from the area of low power digital circuit design, embedded
memory to robust verification architecture in processors. I am currently the
leader of the Berkeley
YODA research group.
RESEARCH INTERESTS
Robust low-power design for nanometer
CMOS technology
- Ultra-low power design techniques for circuits and architectures
- Error-tolerant designs and correction techniques for VLSI circuits and
memories
- Circuit and system design methodologies in the presence of statistical
variations
Design and optimization of embedded
memory
Development of robust and
power-efficient verification architecture for fault tolerance in modern
processor
UC Regents
Fellowship at University of California, Berkeley, 2000 - 2001
Scholarship
for Exceptional Academic Performance at Tsinghua University, China 1999 -
2000
PUBLICATIONS
"Ultra Low Power Circuit
Design", Book chapter in
Nano-CMOS Circuit and Physical Design,
to be published by John Wiley
& Sons Inc., 2004.
Papers
[1] H.
Qin, Y. Cao, D. Markovic, A. Vladimirescu, and J. Rabaey, "Standy supply
voltage minimization for deep sub-micron SRAM", IEEE
Microelectronics Journal, Aug 2005, vol. 36, pp. 789-800
