Design Flows for Single Chip Radios

The central focus of my research is to develop a design methodology for integrated radios.  Right now, I'm focusing on the problem of pulling together a myriad of different CAD tools into a working design flow.  Here are some links that detail our progress.

• IC Design Flow Research Page
• SSHAFT Manifesto

DSSS TDMA Baseband Transceiver

This chip implements coherent timing recovery for the TCI-PicoRadio project [1].  The chip has 600k transistors and is designed to run at 25 MHz and consume 21 mW at 1V.  This chip demonstrates several new aspects of our flow: gated clocks (5 clock domains!), Stateflow-VHDL translator (40 states in 4 machines), and design without full-chip simulations below the level of Simulink [2].  The design work was done primarily by Josie, with some help from Mike (coarse timing acquisition block) and Tufan (transmitter).  Tina developed the clock-tree insertion flow used for the design.  Go Team!

[1] J. L. da Silva, et al, “Design methodology for PicoRadio networks,” Proc. of the Design, Automation and Test in Europe, pp. 314-23, March 2001.
[2] W. R. Davis, et al, "An Automated Design Flow for Low-Power, High-Throughput Dedicated Signal Processing Systems," Proc. of the Asilomar Conf. on Signals, Systems and Computers,  Nov. 2001.

SOVA Chip

The Soft-Output Viterbi Algorithm (SOVA) has been recently examined as a building block in iterative decoders for high-speed magnetic storage.  These decoders promise significant bit-error performance improvement over conventional decoders at the expense of increased complexity.  This chip includes inner and outer decoder building blocks for an iterative decoder and uses a novel register-exchange method for calculating survivor paths [1].

This chip was the first to pass through our design flow with a single phase clock!

[1] E. Yeo, et al, “VLSI architectures for iterative decoders in magnetic recording channels,” IEEE Trans. on Magnetics, vol. 37, pp. 748-55, March 2001.

Parallel Decimation Filter

This chip was a portion of a larger design which included the timing-recovery subsystem for the same CDMA system which inspired the CDMA Channel Estimator chip described below.  Part of the system included a massively parallel decimation filter for a sigma-delta ADC used as part of the phased-locked loop.  This was mainly intended to be a short-cut to implementation, but it became a great test-case for the automated design-flow which has become the focus of my research.

This chip was the first to pass through the "push-button" silicon assembly flow (recently named SSHAFT) in April 2000.  The design was done entirely in Simulink by Paul, except for the floor-plan which was created with Cadence's Design Planner by me. The automated flow began with the generation of an EDIF file from the Simulink view by a home-grown netlisting tool developed by Hayden called BCC. The modules were developed by Ben and Dave, the flip-flops by Fred, and the clock drivers by Dejan.  Kevin developed a tool called sf2vhd which translates Stateflow blocks in Simulink into synthesizable VHDL code.  I was responsible for the synthesis (Design Compiler), floor-planning, place & route (QPlace and IC Craftsman), and physical verification flows (Calibre), as well as all of the automation and new technlogy files.  Other verification flows were developed by Fred (logic with TimeMill), Ning (timing with PathMill), and Dejan (clock-tree with Arcadia and Spectre).  Some details about the chip are available on the slides from my presentation and poster at the BWRC Summer 2000 Retreat.

The chip was designed in ST's 0.25 um technology for 1V 25 MHz operation and a power dissipation of 10 mW.  It contains 300K transistors and has a die size of  3.5 x 3.0 mm.  It's currently under test.  The scan-chain works... I'll post more as it comes in.

CDMA Channel Estimator

One of our goals in the Single Chip Radio group is to show that Multi-User detection can be performed with low enough power to be feasible in portable wireless devices.  This chip is the first step towards realizing this goal.  It will contain the circuitry to receive and synchronize to a digital baseband CDMA signal and estimate up to 4 multi-path components.  The demodulator circuitry will be left off for this test-chip. 

The logic design of the chip was performed by Ning, Hungchi, Mehul, and Brian.  I was responsible for chip assembly and verification and developed most of the design flow.   It was designed in a 6-metal 0.25 um CMOS process, contained 400K transistors, and had a die size of 4.6 x 3.4 mm... definitely the biggest project I've ever been a part of! 

Serial EEPROM Interface

I designed this circuit in the summer of 1997 to help Anthony Stratakos finish his Ph.D.  The circuit consisted of a custom SRAM designed in Magic and an interface to a NM93CS06L serial EEPROM chip designed with Cadence and Synopsys.  Part of the design was synthesized from VHDL and the rest designed by hand, using the standard cell library developed here by Tom Burd.  Cell Ensemble was used for placement and routing.  It was then imported back into Magic for extraction and simulation with EPIC TimeMill.  As you can probably tell from the Frankenstine-like description, this circuit was my introduction to ASIC design and the various Cadence tools. 

Tony's chip was a very high-efficiency DC-DC converter which was the focus of his research.  My little support circuit was an island of synthesized standard cells in a sea of full custom layout.  The chip was fabricated in the fall of 1997 in the 0.6 um HP 3-metal process through MOSIS. 
 
Give me some time to get some pictures up here... 
 

Quad Chua's Circuit Chip

The real challenge of this chip was designing it to be robust against process variations.  I wanted each circuit to be "self-biased" in the chaotic operation region, but this region is a very slim range of capacitor values and transconductances.  To do this, I made all diff-pair and bias current transistors 4 times longer than necessary and used common-centroid layout techniques.  As a result, nearly every chip had at least one circuit properly self-biased. 

Another challenge was designing for a low supply voltage of +,-3V.  When scaling down bias current and keeping transistor dimentions and transconductance constant, V_GS increases.  So, in order to run at the lower supply voltage, I had make make some of the bias transistors insanely wide (ca. 2mm) and work with very tight margins of error.  As you might imagine with such large transistors, this was a rather low-frequency circuit.  Some of the OTA's had first-pole frequencies at about 50 kHz. 

For more information, see part II of my Master's report below, or for a quick introduction, see my old chaos research page. 

MATLAB to RTL Synthesis

This project  from the fall 1998 semester presented a first look at the possibilities of synthesis paths from various MATLAB descriptions. 

• Project Page

Architectures for Wideband CDMA Software Radios

This project, also from the fall 1998 semester, examined the feasibility of implementing the baseband digital signal processing for a Wideband CDMA radio with general purpose processors.  The processors investigated were the experimental Vector IRAM from Prof. Patterson and the the Pleiades architecture from Prof. Rabaey. 

• Project Page

Comparison of Low-Swing Driver/Receiver Circuits for Reconfigurable Interconnect

In the spring of 1997, I participated in a class project to invesitgate low-swing global interconnect schemes to see how well they would contribute to Prof. Rabaey's Pleiades architecture. 

• Presentation slides (311k PS file)
• Final Report (HTML)