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About My Research...
last updated 8/8/96
My research deals mainly with IC design of chaos generators.
I'm kind of in-between projects, right now,
and attempting to define a masters project which will get me back on
track academically. If you have trouble understanding any of what's
said here, then try reading The Chaos Page. It
describes many of the terms and concepts here in more detail.
In order to let people better investigate applications of chaos, we need
to keep churning out chaos generators for people to study, and putting
them on a chip is a good way to make them small, simple, and repeatable
(although not cheaper, at this point). What makes a good chaos
generator?
- Chaotic Transient - When left alone, the circuit must have a
neither an AC nor a DC solution. The solution must be a strange
attractor.
- Allow for Feedback - Many applications of chaos depend on
circuits which synchronize, i.e. they must be connected in
a manner that causes them to follow the same solution. This occurs when
there is negative feedback from a difference signal. Thus, the chaos
generator can't just send out its signal. It has to accept signals as
well.
- Consistent Parameters - In order for the generators to
synchronize, they must have nearly identical parameters. Mismatch
between the circuit elements introduces noise into the application they
were meant for.
The two chaos generators which I have dealt with are the famous
Chua's circuit and the chaotic APLL. I'll talk a little
about each one here.
Chua's Circuit
The only project I've really completed is to make a chip with 4 of these
circuits. This circuit was created more than 10 years ago and pretty
much set the modern trend off chaos research in electrical engineering.
It is the ``canonical'' chaos generator.
A schematic of the circuit appears below. It's pretty simple,
consisting of two capacitors, one inductor, and a non-linear element
called the Chua diode by some. The I-V curve of the Chua
diode appears below as well. It's simply a negative resistor which
saturates to a lower value at a certain breakpoint voltage. This is
pretty easily implemented with two transconductance amplifiers connected
in parallel. These figures are reprinted from the article by José
Cruz referenced below.
When the differential equations for this circuit are written down, we
find that the system is third order with the state variables
V1, V2, and IL. Depending on the values
chosen for C1, C2, R, L, and the Chua diode
parameters, the solution could be DC, AC, or a strange attractor.
Volumes have been written about the different solutions, but the one
which people seem to use the most is the double scroll attractor
which is shown below. In these plots, V1 is x,
V2 is y, and IL is z. The top two
plots show the attractor from two different angles.
The bottom plots show the
V1 signal in the time and frequency domains.
Here is the layout of the chip I designed. It was intended to be low
power, and as such uses a rather small frequency band (about 2 kHz). It
was fabricated by MOSIS using a 0.8um CMOS process at Hewlett-Packard
for a cost of about $6000. It contains four of Chua's circuits
all operating in the double scroll region. The design was
largely taken from the chip designed by José Cruz.
For anyone who wants to know more about Chua's circuit or IC
implementation thereof, check out the following papers.
Leon O. Chua, ``Chua's Circuit: An Overview Ten Years Later'',
Journal of Circuits, Systems, and Computers Vol. 4, No. 2 (1994)
pp 117-159.
José M. Cruz and Leon O. Chua, ``An IC chip of Chua's
circuit'', IEEE Transactions on Circuits and Systems II: Analog and
Digital Signal Processing Vol. 40 (1993) pp 696-701.
Chaotic APLL
The chaotic APLL is simply an analog phase locked loop with parameters
chosen so that cycle skipping occurs. It was discovered by Géza
Kolumbán and Béla Vizvári that one can get strange
attractors with this circuit. A block diagram of the circuit appears
below along with a bode plot of the loop gain required for the APLL to be
chaotic (reprinted from the article by Kolumbán and Vizvári
which is referenced below).
The unique thing about the chaotic APLL is that it produces band
pass chaos. You can see from the figure above that Chua's
circuit produces a signal which is centered around 0 Hz. It is a
base band signal. But the chaotic APLL produces a signal which
is limited to a narrow, high frequency band i.e. band pass.
This is useful in that it eliminates the need for a second layer of
modulation if the circuit were used in some sort of wireless
communication system. Not only is the second layer more expensive, but
it introduces noise which makes it more difficult for circuits to
synchronize. The chaotic APLL effectively eliminates a noise source.
Also, some chaos communication schemes depend on the statistical
properties of the signal (such as DCSK, described below). Most
secondary modulation schemes rely on changing the signal to make it more
noise resistant (such as Frequency Modulation). This could destroy the
statistical properties of the chaotic signal. The chaotic APLL
eliminates this problem as well.
As for now, this is all I've really done with the chaotic APLL. More
later if anything comes of this lead. For those interested in reading
it for themselves, check out the following paper.
Géza Kolumbán and Béla Vizvári, ``Nonlinear
Dynamics and Chaotic Behaviour of the Analog Phase-Locked Loop'',
Proceedings of the International Conference on Nonlinear Dynamics
of Electronic Systems (NDES) 1995 pp 99-102.
William Rhett Davis
wrdavis@eecs.berkeley.edu
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