1 Introduction

Figure 1: General Interconnect Network Model

Figure 2: Circuit Diagram for Performance Analysis

This report seeks to answer the following questions:

• Can low swing interconnect reduce power?
• Can methods be found to handle the problem of noise?
• How much area would such an interconnect scheme need?
• Are the interconnect schemes examined in this report feasible, in the long run?

2 System Design Analysis

Because the interconnect must support a self-timed signaling scheme, our noise requirement is that the system must be glitch free. Glitching is caused by noise spikes which vary in size depending on wire capacitance, coupling capacitance, wire resistance, signal swings and rise/fall times. With the exception of signal characteristics, all of these parameters can be calculated when given the line pitch, line width, and pass transistor geometry. We therefore assume in this section that signals can be described by a voltage swing and a rise/fall time. These parameters are considered design criteria for the line drivers and otherwise have no effect on area and coupling noise. We must also assume that the receiver can be described by a parameter V_Pmax, which represents the size a noise spike must reach before becoming a glitch.

We will begin by discussing the layout of the programmable interconnect matrix which we used to derive our basic model. Then, we will discuss our methods for determining coupling capacitances. Lastly, we will describe how we cope with coupling noise and supply noise

2.1 Programmable Interconnect Matrix (PIM) Layout

The term programmable interconnect matrix (PIM as opposed to PIP) stems from the fact that only one memory cell is needed for a number of bit-lines. Area must be set aside for the memory, but the memory circuit will be inactive during normal operation and will thus not contribute to coupling noise. A memory cell could be made out of metal1 and poly-silicon alone and tucked under metal 2 wires. Since global wires are assumed to take up large area, the memory area is considered to be negligible.

Figure 3: Four Bit PIM Layout

2.2 Methods for Calculating Coupling Capacitances

Figure 4: Parasitic Lateral Capacitances

C_c = [k₁ + k₂(1 - e^-w/m)](S/h)^-n (1)

The values for the parameters above were chosen with consideration to typical values for an HP 0.6um CMOS process supplied by MOSIS. Therefor the following values are obtained from [7]:

k1 = 4.69e-5 pF/um

k2 = 3.96e-5 pF/um

m = 2.35 um

n = 0.83

h = 1um

Figure 5: Coupling Capacitance as a Function of Spacing and Width

Figure 6: Coupling Capacitances of Architecture

The coupling capacitance induced between two wires of width 2um in the same metal and spaced 10um apart is 10pF/um. The total orthogonal capacitance experienced by one bit line of width 2um is (51*142) = 7.2fF/um. The capacitance induced by all of the orthogonal wires is insignificant in comparison to that produced by the neighboring wire. Therefor for simplicity purposes, coupling capacitances between two wires in the same metal will be furthered explored as potential noise sources.

2.3 Methods for Handling Coupling Noise

Figure 7: Coupling Noise Model

(2)

Using this model, we can assume a linear superposition of all noise sources. We can make this model more general if we do not assume that the initial value of V is zero. In this case, the voltage will be in the process of settling to its final output value. To ensure that no glitch is possible, we must show that the derivative of V(t) can never be positive when in the transition region. This requirement reduces to the following expression:

(3)

The value of R will tend to be dominated by either the pass transistors or the line driver, both of which are non-linear resistances. A minimum-sized inverter was simulated in the HP 0.6 um process and found to have a resistance ranging from 25 kOhms (for Vout=1.5 V) to 5 kOhms (for Vout=0 V).

To illustrate the use of this model, consider the example of noise coupling between two adjacent global wires. The wires are 2mm long and 1.2 um apart. Using the methods presented in section 2.2, we calculate the coupling capacitance to be 60 fF/mm. The pass transistor is assumed to be a transmission gate with the PMOS and NMOS both 20um wide. The majority of the resistance is assumed to come from the CMOS inverter in steady state, thus giving R a value of 5 kOhms. The total line capacitance include the local wires and transistor parasitics is calculated to be 390 fF. The single line is simulated and found to have a rise rate of 115 mV/ns. Using this data, we can compute the following:

The success of this model in predicting the noise from a neighboring wire shows that lumping distributed noise contributions into one node can greatly simplify the noise analysis. These equations can be used to gain an intuition about how to design a system which is coupling noise resistant. Please note that assumptions were made about film thicknesses to calculate coupling capacitance in spite of sketchy data on the HP 0.6 um process. The induced noise peak in this example may not be entirely accurate.

All that remains is to measure V_Pmax for each receiver circuit. A glitch is defined as an erroneous transition. We can further define an erroneous transition as an intermediate output. Thus, V_Pmax for a given receiver circuit will be the change in input voltage required to produce an output of V_IL or V_IH.

To summarize, a method has been created for estimating the resistance of the interconnect to coupling noise. This method requires extraction of resistance and capacitance values from a layout and an approximation of the line driver output resistance. The method also requires a priori knowledge of the noise signal's voltage swing and rise/fall time. The receiver circuit sensitivity to noise is accounted for in the V_Pmax term. Using this method, we will evaluate the noise performance of different driver and receiver circuits.

2.4 Methods for Handling Supply Noise

Unfortunately, our project group has had very little experience with this subject and has not performed an adequate analysis. In order to predict what kind of supply noise is caused by our circuits, however, we have measured the peak supply current drawn during transitions. This data will help us see how much care must be taken in designing the power distribution system.

3 Driver/Receiver Circuit Analyses

Designs for low swing driver/receiver circuits fall roughly into two categories. First, there are the circuits such as the Hitachi architecture which use extra supply rails to limit the swing. This architecture is limited in that it needs low-threshold transistors to function properly. Second, there are the precharged circuits, such as the "Precharged to half Vdd" scheme, which rely on special signaling to initialize and limit the swing on the wires. Both the Hitachi and "precharged to 1/2 Vdd" scheme will be examined in this section.

We had intended to also analyze a differential driver/receiver pair but due to the complexity of the circuit, we did not provide performance analysis. The differential circuit uses reduced swing supply rails in addition to a precharging scheme. This circuit will be discussed briefly followed by a summary of the circuit performances.

3.1 CMOS Inverter Chain

We found that the delay and switching energy depend almost entirely on the total line capacitance, independent of where local wires intersect the global wires. As one might expect, increasing the transmission gate widths gives an optimum in terms of delay, at the point where resistance becomes insignificant and parasitic capacitances dominate. Also, varying the number of hanging transmission gates connected to the wire has a major effect on delay and energy.

Figure 8 shows delay and switching energy plots for a 5 mm wire while varying the combined NMOS and PMOS widths. A two-stage, progressively sized CMOS buffer with a scaling factor of 5 was used for these simulations. The single processor case considers no hanging drains from pass transistors of unconnected processors. Increasing the number of processors in the system increases the number of drain capacitances which must be switched. There will be two extra drains per processor: one for the driver and one for the receiver.

Figure 8: CMOS Inverter Performance vs. Pass Transistor Size (for a 5mm wire)

Figure 9: CMOS Inverter Performance with Bootstrapped Gate NMOS Pass Transistor (for a 5mm wire)

3.2 Hitachi Low-Swing Architecture

Figure 10: Hitachi Low-Swing Driver/Receiver

1. to achieve a high speed level conversion both from high to low and low to high
2. to achieve low standby current as compared to base case which results in ove rall reduced energy

Source Offset Driver

Sense Amplifier

The reduced output drive current of the driver contributes to the delayed response of the receiver. As a result, the increase in conversion delay added by the receiver becomes significant. Though some of the conversion penalty can is compensated by the reduction in interconnect delay.

Figure 11: Illustration of receiver's operation

3.2.1 Using low threshold transistors

Our goal is to optimize for energy while minimizing the delay, therefor sizes will be chosen which optimize the energy delay product. Performance is then evaluated by setting the interconnect length to 5mm and varying the swing between 0.7V to 1.5V. The simulated results are tabulated in Table 3. A signal with a 0.8V swing reduces the energy by 1/3 (swing of 1.5V) but with a propagation delay that is 15% of its 50ns period. Table 4 demonstrates that the swing with the best Energy Delay Product (EDP) is in fact full swing, though it has the highest energy consumption.

The effect of wiring capacitance and resistance is simulated as shown in Figure 14. This scheme is quite insensitive to distributed RC increases as the delay and energy increase proportionally. This is due to the small ratio of the interconnect delay to that of the entire scheme. The length must the become quite large before it can begin to dominate the delay. The operation of this scheme can then be maintained as long as the distributed RC is smaller than the interconnect delay.

3.2.2 Using standard transistors

The simulated effects of the voltage swing and length are in Figure 17 and Figure 18. Table 6 summarizes the results.

	Voltage Swing	Average Delay	Average Energy	Average Energy*Delay
Lowest Energy	0.9 V	7 ns	2 pJ	1.4e-20 Js
Lowest Delay	1.5 V	2.5 ns	3.3 pJ	1e-20 Js
Lowest Energy*Delay	1.5 V	2.5 ns	3.3 pJ	1e-20 Js

3.2.3 Voltage Scaling

V_sl and V_cl will be generated on chip using the main supply, therefor examining the effect of these supplies on the overall performance provides a better approximation of the actual power dissipation. The supplies can be generated in order to attain the desired voltage through the use of voltage converters. Such converters can be divided into two main groups : linear and switching regulator. Though there are many variations of the two, we are interested in overall efficiency of the converter. The linear regulator can be modeled as a resistor network which divides the voltage. As the new voltage becomes much smaller than the supply, the efficiency of the linear regulator will begin to decrease. The efficiency of such supplies is usually about 80% [10].

The switching regulator, also called a pulse width modulator is able to provide a higher efficiency, but the overhead is much greater than that of the linear in terms of area and complexity. The efficiency of this regulator is in the range of 90-95% [10].

Therefor the energy measurements provided above can be modified to exhibit the behavior of either regulator by adding the inefficiency of the supply which is be a function to the swing desired.

3.2.4 Summary of Results

Table 7 compares the performance of the two cases using the optimized versions of each one.

Due to factors such as conversion delay and the RC effects of the interconnect proposed, the advantages of this architecture would be best achieved at lower frequencies. The reduced supply (1.5V) decreases the output current drive of the driver which contributes to the conversion delay of the receiver. An additional overhead in terms of voltage regulators are needed which have tradeoffs in terms of power, area and complexity. The linear regulator is the least complex, but is more inefficient while the switching regulator is more complex and uses more area but results in a more efficient conversion.

The proposed architecture is intended to operate with a supply of 2 Volts, but we were interested in evaluating its performance at 1.5V because speed degradation may not be large enough to hinder the operation of the type of low power application in which it may be utilized. Using low threshold transistors may have improved the overall performance of the scheme, but for feasibility purposes, the scheme was examined without low thresholds. The delay increases as expected, but only enforces the fact that this scheme cannot operate at high frequencies with reduced voltage supply Vdd.

3.3 Precharged to Half V_dd Scheme

Figure 19(a): Single-Ended precharged driver/receiver

Figure 19(b): Timing diagram of single-Ended precharged driver/receiver

The circuit is performed as follows. During the precharging phase, the input of the precharging inverter (M3-M4) is short-circuited to the input so that the inverter is forced to its switching point (Vdd/2) when M3 and M4 are appropriately sized. During the evaluation phase, the short-circuit is disabled, and the interconnect capacitance is charged up or discharged according to the input. The interconnect swing depends on the current through M1 M2 (i.e., the sizes of M1 and M2), the interconnect capacitance, and how long evaluation signal is high. The reduced interconnect swing results in a large output swing since the output inverter acts as an amplifier.

In our midterm report, we promised to examine this circuit with M3 and M4 at the driver instead of the receiver. This would allow the driver to handle all precharging. Such a modification does not work, however, because the gate voltage rises too quickly to the median value and reduces the precharge current to a trickle. Therefore, M3 and M4 must be at the receiver.

Several important design issues for optimizing this circuit need to be addressed:

1. The interconnect swing are approximated by

   (5)
   

   Thus, swing can be adjusted mainly by changing the sizes of M1 and M2, and the evaluation period. It can be also adjusted by changing the sizes of M3 and M4 (i.e., changing the C_int)

2. The total delay is the sum of the delay through NAND(NOR) gate, delay through M1 and M2, delay through interconnect, and delay through M3 and M4. The portion of delay due to NAND(NOR) could be significant and need to be reduced by sizing up the transistors, however, in the cost of increasing the circuit area.

3. The total power dissipation can be broken up into four categories as described below:
   • precharge power dissipation which is attributed to the static current through M3 and M4 during precharge phase, and is given by

     (6)
     

   • dynamic power dissipation attributed to the interconnect charge switching and the interconnect swing during evaluation phase, and is given by

     (7)
     

   • static power dissipation which comes mostly from the leakage current after the evaluation phase and before the next precharge signal.

   • standby power dissipation, the power dissipation when none of the precharge, evaluation, or input signal occurs. For instance, when bus line is inactive, the only power dissipation is caused by standby power.

4. The switching threshold of INV1 has to be significantly below half- V_dd to reduce the power dissipation of INV1 during percharged phase. It can be achieved by properly sizing the INV1.

5. The sizes of M3 and M4 are selected so that the switching point is in the middle of the V_dd. The large sizes of M3 and M4 are desirable in order to amplify a small swing and meet the delay constraints. However, it will increase the precharge power dissipation while decrease the dynamic power dissipation because the swing is reduced by sizing up M3 and M4.

Since this circuit is depending upon the operating frequency, the implementation of this circuit in the reconfigurable interconnect scheme is complicated by the fact that our project is geared towards locally synchronous , globally asynchronous, data driven interconnect, that is, each processor may be operated under different frequency and voltage. Therefore, the challenge is how to combine data-driven asynchronous communication at the protocol level with a simple self-timed signal which provides a signaling scheme that is not dependent upon the operation clock.

We propose a modified circuit as shown in Figure 21a, in which the precharging signal is self-timed and sent by the handshaking ACK signals from the previous communication. Instead of using an evaluation clock, the evaluation signal is triggered by the input signals, and enables the evaluation phase. The timing diagram for this precharged to half-V_dd circuit is shown in Figure 21b.

Figure 21a: Modified precharged driver/receiver scheme

Figure 21b: Timing diagram for the precharged circuit

Several optimization issues are addressed as follows:

1. The periods of handshaking request and acknowledge signals are determined by the wire delay. In the extreme case which bus length is 10mm, wire delay is approximately 2.5ns and thus the precharge period is about 5ns which is sufficient for precharging.

2. While this self-timed precharged interconnect scheme is feasible, its potential has not yet been fulfilled because of its non-zero standby power dissipation. Note that this reconfigurable bus is often inactive and a "zero-power" standby operation is critical for a low-power application. It can be explained by the fact that the bus lines still stay at half V_dd during the standby period (communication inactive period). Hence, we choose the minimum sizes of M3-M4 and INV1 to reduce the possible standby power dissipation.

Therefore, we propose another self-timed precharged interconnect scheme to improve the standby power dissipation, as presented in Figure 22a. As can be observed, a precharged signal is synchronized by input signal while a sequential evaluation signal is triggered by the precharged signal after the precharging is complete. Figure 22(b) shows its timing diagram.

Figure 22a: Zero standby-power precharged driver/receiver scheme

Figure 22b: Timing diagram for this improved precharged circuit

This improved circuit shows a superior performance in standby power dissipation, as summarized in Table 10. Since ths bus line in this case is set at either 0 or V_dd during the standby period, it essentially comsumes no standby power and thus reduce total power consumption. However, the cost we have to pay is an increased delay time due to the fact that input signal has to wait for the completion of precharging phase in order for the bus line starting to send signal. Fortunately, this additional delay overhead is usually less than 5ns.

It is also worth noting that the bus length is varied due to the nature of the reconfigurable interconnect. Assuming the bus length is ranged from 1mm to 10mm in the case of a 1cm x 1cm chip size, the simulation results show that the total power dissipation only increase 5% while delay increases 37% as bus increases from 1mm to 10mm.

3.4 Differential Scheme

This architecture is intended for very high speed applications and can drive a bus using a differential swing of 100mV with a 1.2V supply [6]. In order to obtain the low swing and operate at a fast rate, precharging the bus to half the level of V_DD during half of the cycle is employed. The driver is composed of switches and an equalizer while the reliever is composed of a current sense amplifier and a gate-receiver. The gate-receiver amplifies the voltage difference between the differential lines. The driver and receiver are synchronized through the use of a main clock (MCLK) and a receiver clock (RCLK). The transferred data is sensed by the receiver when it is clocked by RCLK. It is operated at the same frequency as MCLK, but is delayed by a factor of a quarter of MCLK's cycle.

The driver precharges the complementary lines of each bit to half V_DD during the former half of the cycle and in the latter half the bus switching is controlled by the input data. The bus lines are equalized by using charge-sharing between the two which is attained by shorting both floating lines. The driver uses two additional supplies to generate the desired low swing, similar to the concept of the Hitachi circuit. It also needs to generates the complement of the signal.

To obtain a low-voltage operation, a larger V_GS is generated at input gates of the receiver and output gates of the driver by employing low thresholds CMOSs. Obtaining a larger V_GS helps compensate for the reduction in voltage supply. During the latter half of the RCLK, the internal nodes of the receiver are precharged to half of V_DD. In the former half, any slight voltage deviation from V_DD/2 on the primary inputs will be amplified. This new charge will cause the output to be quickly pulled to high or to ground and for the remainder of the cycle the receiver will continue to sustain the signal at is current level.

Simulations were performed and a handshaking protocol as suggested by the the precharged scheme discussed in section 3.3 would need to be utilized. The most complex portion of this scheme is implementing the multiplexing between neighboring wires which is desirable due to power savings. Preliminary simulations demonstrated the high degree of accuracy required in implementing this scheme. Many high speed switches are required and a third clock, called the data clock (DCLK) would be needed for multiplexing data between neighboring wires. As can be inferred, in order to take advantage of this scheme's benefit, a large amount of overhead is required :

1. The scheme needs to be converted to self-timed using a hand-shaking protocol l.
2. Regulators or additional supplies generate the reduced voltages needed to set the signal swing.
3. Low threshold CMOSs are needed to compensate for the reduced current drive .
4. Data lines are precharged which increases static power consumption.
5. Complementary signal needs to be generated requiring additional circuitry.
6. Multiplexing circuitry is needed, which needs to be combined with the hand -shaking protocol

3.5 Summary

Notes:

1. The driver is the last inverter in a chain of 4 progressively sized inverters. The delay includes the transitions of the entire chain.
2. Assumes 100% efficient switching regulators for low-swing supply rails.
3. Uses a 2.5 V supply instead of 1.5 V. The circuit could not be made to function at lower voltages.
4. Uses the Zero-Standby Power signaling scheme. Delay includes 5 ns for precharging and 3 ns for transmission.
5. Assumes the synchronous timing scheme is used with T_eval = 2 ns.

In retrospect, the circuits we chose to test were intended to increase the speed of interconnect and not to reduce power. The CMOS circuit has the lowest driver resistance and a large V_Pmax, suggesting that it will be the most noise resistant. This circuit tends to induce large current peaks in the supply rails and be energy inefficient for small delays.

The precharged is slightly less noise resistant due to its high driver resistance. This circuit can achieve speeds much greater than the CMOS inverter chain can, but at a large energy cost. This circuit is probably not suited to a low power system, even if the timing problems could be solved.

The Hitachi circuit has an energy advantage over the CMOS inverter for a delay of 5 ns, but uses more energy than the CMOS inverter with a delay of 10 ns. The circuit was difficult to optimize for swings below 1 V, and did not function below 0.7 V. Note that V_Pmax is reduced, meaning that this circuit will be more sensitive to noise. Also, the driver output resistance is huge (500 kOhms), but this may simply be an artifact of our doctored technology file. While the circuit does seem to be significantly more prone to coupling noise, it is important to remember that the rise rate of neighboring bitline voltages will be much smaller for this scheme than for the CMOS inverter.

4 Conclusions and Recommendations

• Can low swing interconnect reduce power?

  Yes, but only for higher switching speeds or with complex signaling schemes. The overhead of the Hitachi architecture causes it to consume more power than the standard CMOS inverter when the total delay is around 10 ns. The power used by precharged schemes depends entirely on the signaling architecture which supports it.

• Can methods be found to handle the problem of noise?

  Coupling noise for the speeds of interest can be modeled and predicted using the methods presented. Layouts can be made noise resistant to an arbitrary degree. The real problem is likely to be supply noise which has not yet been adequately examined.

• How much area would such an interconnect scheme need?

  The area depends on the dimensions of the PIM and the number of PIM's required. Additional area is needed for the global wires. For the 4-channel, 6-processor case, the total area is likely to be around 1 mm².

• Are the interconnect schemes examined in this report feasible, in the long run?

  Probably. The base case system with CMOS inverters operating in full-swing mode seems to be the best of the circuits analyzed for the Pleiades team. This circuit is robust, energy efficient, and relatively noise free for delays around 10ns. But it is still possible that a low-swing architecture exists that will outperform the static CMOS inverter. What will be the characteristics of such an architecture?

  1. Only one extra supply rail - The Hitachi scheme examined would not work unless two extra supply rails were used to put the swing around the midpoint voltage of 0.75 V. If a circuit could be developed which allows the voltage to swing between ground and an intermediate voltage, then the PMOS pass transistors could be eliminated as well as the complexity of a second voltage regulator.
  2. Static receiver with large noise margins - The receiver should be static to support handshaking signals. Making a static level restorer circuit with noise margins equal to half the voltage swing is non-trivial.

5 References

1. Nakagone, Y. et al, Sub-1-V Swing Internal Bus Architecture for Future Low-Power ULSI's, IEEE Journal of Solid-State Circuits, April 1993
2. Shepard, K.L. et al, Noise in Deep Submicron Digital Design, 1996 IEEE/ACM International Conference on Computer-Aided Design,November 1996
3. Okada, T., et al, Characterization of Net Configurations for Multichip Modules, IEEE Multi-Chip Module Conference, July 1994
4. Vassiliou, I. and Prihadi, K., A Comparison of CMOS Driver/Receiver Circuits for Reduced Swing Interconnect, U.C. Berkeley May 1993
5. Rabaey, J.M., "Digital Integrated Circuits : A Design Perspective",copyright 1996, Prentice Hall Electronics
6. Yamauchi, H. et al, A Signal-Swing SUppressing Strategy for Power and Layout Area Savings Using Time-Multiplexed Differential Data-Transfer Scheme, IWWW Journal of Solid-State Circuits, September 1996
7. Lee, M., A Fringing and Coupling Interconnect Line Capacitance Model for VLSI On-Chip Wiring Delay and Crosstalk, IEEE International Symposium on Circuits and Systems, May 1996
8. Sicard, E., Analysis of Crosstalk Interference in CMOS Integrated Circuits, IEEE Transactions on Electromagnetic Compatibility, May 1992
9. Kuroda, T., et al, A High Speed Low-Power 0.3um CMOS Gate Arrat with Variable Threshold Voltage (VT) Scheme, Proceedings of the IEEE Custom Integrated Circuits Conference, 1996