Home Page Massimo Alioto

Massimo Alioto

Associate Professor

Information Engineering Dept.

University of Siena
Via Roma, 56

53100 Siena (Italy)
phone: +39 0577 234632
fax: +39 0577 233602

homepage: http://www.dii.unisi.it/~malioto

e-mail:

Visiting professor

Berkeley Wireless Research Center (BWRC) - UCBerkeley

2108 Allston Way, Suite 200
Berkeley, CA 94704-1302
Fax: (510) 883-0270

homepage: http://bwrc.eecs.berkeley.edu/~alioto

e-mail:

SHORT BIO:

Massimo Alioto was born in Brescia in 1972. He took the M.Sc. degree in Electronic Engineering in 1997, and the Ph.D. degree in 2001 from the University of Catania. In 2002, he joined the Department of Information Engineering of the University of Siena as a Research Associate, and in the same year as an Assistant Professor. In 2005 he is appointed Associate Professor in Italy, and is engaged in 2006 by the Faculty of Engineering of the University of Siena. In the summer of 2007, he was visiting professor at EPFL - Lausanne (Switzerland). In 2009-2010, he is visiting professors at the Berkeley Wireless Research Center (BWRC) at the University of California, Berkeley.

His research interests involve digital integrated circuits, both at the transistor and gate level, the development of efficient models and design strategies, with emphasis on high-performance and low power consumption. In particular, the research activity has been devoted to MOS Current-Mode Logic, low-power and ultra low-power circuits (such as adiabatic logic), optimized design of several arithmetic and logic units (e.g., adders, high fan-in multiplexers), design of cryptographic circuits that are robust against DPA attacks, modeling and design of CMOS circuits tolerant to variability and with low leakage, interconnect modeling, True and Pseudo-random number generators for cryptographic applications, bipolar emitter-coupled logic.

He is author or co-author of more than 140 papers on international journals (50, mostly IEEE Transactions) and international conferences. Two of them are among the 25 most downloaded IEEE TVLSI papers in 2007 (respectively the 10^th and 13^th). He is also coauthor of the book "MODEL AND DESIGN OF BIPOLAR AND MOS CURRENT-MODE LOGIC: CML, ECL and SCL Digital Circuits" (Springer). Currently, he is an IEEE Senior Member.

Since 2001 he has been teaching several courses on Basic Electronics, Microelectronics, Digital VLSI Electronics at University of Catania and Siena, other than the post-graduate master "Sicurnet". He has also given several invited seminars in several faculties throughout Europe. He is the director of the Electronics and Measurements Lab in the Engineering faculty of Siena (site of Arezzo).

In 2008, he is nominated Distinguished Lecturer by the IEEE Circuits and Systems Society for years 2009 and 2010. In 2009 he is invited speaker for the tutorial “MOS Current Mode Logic VLSI Circuits: from High-Speed to Ultra-Low Power Design” at the international conference ISCAS 2009 (May 2009 - Taipei, Taiwan), jointly with prof. Yusuf Leblebici (EPFL, Switzerland). In the same year, he is invited speaker for the tutorial “Design of nanometer MOS Current Mode Logic: from very high-speed down to ultra-low power” at the international conference ICM 2009 (Dec. 2009 - Marrakech, Morocco), and the tutorial “Pushing the Limits of Energy Consumption: Opportunities and Challenges in Subthreshold Logic” at the international conference ICECS 2009 (Dec. 2009 – Hammamet, Tunisia). In 2008, he is invited speaker for the tutorial “Design of nanometer MOS Current Mode Logic: from ultra–low power to very high speed circuits” at the international conference APCCAS’08 (Macao, China), the tutorial “Pushing the limits of energy consumption: opportunities and challenges in subthreshold logic” at the international conference ICM’08 (Dubai, UAE).

He is Associate Editor of the following international journals:

- IEEE Transactions on VLSI Systems (2009-present)

- Microelectronics Journal (2008-present)

- Integration, the VLSI Journal (2008-present)

- Journal of Circuits, Systems, and Computers (2007-present)

and Guest Associate Editor of IEEE Trans. on Circuits and Systems – part I for the special issue on best papers selected at ISCAS 2008. He is also Guest Editor of the special issue on “High speed random bit generators” of the International Journal of High Speed Electronics and Systems (2008). He is also member of the Editorial Advisory Board of the Microelectronics Journal.

In 2008, he is Chair Elect of the “VLSI Systems and Applications” Technical Committee of the IEEE CAS Society.

He (or will be) is also Track Chair of the “Logic and Circuits” track of the ICCD 2010 conference, of the “VLSI Systems and Applications” track (200+ paper reviews) of the ISCAS 2009 and 2010 conference, of the “Circuit design” track of the ICM 2009 conference, and in 2007 he is Track Chair of the "Digital circuits" track in the Technical Committee of ICECS Conference.

He regularly serves as member of the Technical Program Committee of various conferences, such as ICM, ICCD, PATMOS, Computer Design & VLSI Symposium 2009 (a part of CSIE). In 2009, he chairs the invited special session “Sub-Threshold Design for Ultra Low Power and Ultra-Dynamic Voltage Scaling” at ISCAS 2009, and the special session “Emerging technologies for nanometer VLSI circuits and applications” at ISCAS 2010. From 2004 he chairs regular sessions at a number of conferences (ISCAS, ICECS, ECCTD, ICM, …).

Since 2000 he is a very active reviewer (70+ papers per year) for several IEEE and IEE journals and conferences (ISCAS, ICECS, IECON, PATMOS, ECCTD).

RESEARCH INTERESTS:

· Low-Power and ultra-low power nanometer circuits

· FinFET logic circuits (BB techniques to enhance the efficiency of the leakage-delay tradeoff)

· Analysis and modeling of variability and leakage in sub-100 nm CMOS technologies

· Optimized design of nanometer arithmetic and logic circuits at the gate level

· Design of VLSI circuits in emerging technologies

· MOS Current-Mode Logic (MCML) circuits: modeling and design

· Low-standby current cache memories based on charge recycling

· Design of circuits for cryptography (resistant against Differential Power Analysis attacks, Random and Pseudo-random number generators based on chaotic maps)

RECENT PUBLICATIONS (SINCE YEAR 2006) - to get the full list, click here

International journals

M. Alioto, G. Palumbo, "Design strategies of Cascaded CML Gates," IEEE Transactions on CAS - part II, vol. 53, no. 2, pp. 85-89, Feb. 2006.

T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "A Feedback Strategy to Improve the Entropy of a Chaos-Based Random Bit Generator," IEEE Transactions on CAS – Part I, vol. 53, no. 2, pp. 326-337, Feb. 2006.

T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "Low Hardware Complexity PRBGs Based on a Piecewise-Linear Chaotic Map," IEEE Transactions on CAS – Part II, vol. 53, no. 5, pp. 329-333, May 2006.

M. Alioto, A. D. Grasso, G. Palumbo, "Design of Cascaded ECL Gates with a Power Constraint", IEE Electronics Letters, vol. 42, no. 4, pp. 211- 212, 16th February 2006.

M. Alioto, G. Palumbo, M. Poli, "Energy Consumption in RC Tree Circuits", IEEE Trans. on VLSI Systems, vol. 14, no. 5, pp. 452-461, May 2006.

T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "The Digital Tent Map: Performance Analysis and Optimized Design as a Source of Pseudo-Random Bits," IEEE Transactions on Instrumentation and Measurement, vol. 55, no. 5, pp. 1451-1458, Oct. 2006.

M. Alioto, L. Pancioni, S. Rocchi, V. Vignoli, "Exploiting Hysteresys in MCML Circuits", IEEE Trans. on Circuits and Systems - part II, vol. 53, no. 11, pp. 1170-1174, Nov. 2006.

M. Alioto, R. Mita, G. Palumbo, "Design of High-Speed Power-Efficient MOS Current-Mode Logic Frequency Dividers", IEEE Trans. on Circuits and Systems - part II, vol. 53, no. 11, pp. 1165-1169, Nov. 2006.

M. Alioto, G. Palumbo, "Power-Aware Design Techniques for Nanometer MOS Current-Mode Logic Gates: a Design Framework," IEEE Circuits and Systems Magazine, vol. 6, no. 4, pp. 40-59, 2006.

M. Alioto, G. Palumbo, "Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison," IEEE Trans. on VLSI Systems, vol. 14, no. 12, pp. 1322-1335, Dec. 2006.

M. Alioto, G. Di Cataldo, G. Palumbo, "Mixed Full Adder Topologies for High-Performance Low-Power Arithmetic Circuits," Microelectronics Journal, vol. 38, no. 1, pp. 130-139, Jan. 2007.

T. Addabbo, M. Alioto, A. Fort, A. Pasini, S.Rocchi, V. Vignoli, "A Class of Maximum-Period Nonlinear Congruential Generators Derived From the Rényi Chaotic Map", IEEE Trans. on Circuits and Systems - part I, vol. 54, no. 4, pp. 816-828, April 2007.

M. Alioto, G. Palumbo, "Interconnect-Aware Design of Fast Large Fan-In CMOS Multiplexers," accepted to IEEE Trans. on Circuits and Systems – part II.

M. Alioto, L. Pancioni, S. Rocchi, V. Vignoli, "Power-Delay-Area-Noise Margin Trade-offs in Positive-Feedback Source-Coupled Logic Gates," accepted to IEEE Trans. on Circuits and Systems – part I.

M. Alioto, G. Palumbo, "Very Fast Carry Energy Efficient Computation based on Mixed Dynamic/Transmission-Gate Full Adders," accepted to IEE Electronics letters.

M. Alioto, G. Palumbo, "Power-Aware Design of Nanometer MCML Tapered Buffers," accepted to IEEE Trans. on Circuits and Systems – part II.

M. Alioto, G. Palumbo, M. Poli, "Analysis and Modeling of Energy Consumption in RLC Tree Circuits," IEEE Trans. on VLSI Systems, vol. 17, no. 2, pp. 278-291, Feb. 2009.

M. Agostinelli, M. Alioto, D. Esseni, L. Selmi, "Leakage-Delay Tradeoff in FinFET Logic Circuits: a Comparative Analysis with Bulk Technology," in print on IEEE Trans. on VLSI Systems.

M. Alioto, M. Poli, S. Rocchi, “Differential Power Analysis Attacks to Precharged Busses: a General Analysis for Symmetric-Key Cryptographic Algorithms,” in print on IEEE Trans. on Dependable and Secure Computing.

A. Tajalli, M. Alioto, Y. Leblebici, “Improving power-delay performance of ultralow-power subthreshold SCL circuits,” IEEE Trans. on Circuits and Systems – part II, vol. 56, no. 2, pp. 127-131, Feb. 2009.

M. Alioto, M. Poli, S. Rocchi, “A general power model of Differential Power Analysis attacks to static logic circuits,” in print on IEEE Trans. on VLSI Systems.

M. Alioto, G. Palumbo, M. Pennisi, “Understanding the Effect of Process Variations on the Delay of Static and Domino Logic,” in print on IEEE Trans. on VLSI Systems

M. Alioto, L. Giancane, G. Scotti, A. Trifiletti, “Leakage Power Analysis Attacks: a Novel Class of Attacks to Nanometer Cryptographic Circuits,” in print on IEEE Trans. on Circuits and Systems – part I

M. Alioto, G. Palumbo, M. Poli, “Simple and Accurate Modeling of the Output Transition Time in Nanometer CMOS Gates,” in print on International Journal of Circuit Theory and Applications

T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, “A variability-tolerant feedback technique for throughput maximization of TRBGs with predefined entropy,” in print on the Special Issue “Advances in oscillator analysis and design” of the Journal of Circuits, Systems, and Computers

M. Alioto, E. Consoli, G. Palumbo, “Flip-Flop Energy/Performance versus Clock Slope and Impact on the Clock Network Design,” in print on IEEE Trans. on Circuits and Systems – part I

M. Alioto, E. Consoli, G. Palumbo, “General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space,” in print on IEEE Trans. on Circuits and Systems – part I

M. Alioto, “Understanding DC Behavior of Subthreshold CMOS Logic through Closed-Form Analysis,” in print on IEEE Trans. on Circuits and Systems – part I

International conference proceedings

T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "Uniform-Distributed Noise Generator Based on a Chaotic Circuit", Proc of IMTC 2006, pp. 1156-1160, Sorrento (Italy), April 2006.

M. Alioto, G. Palumbo, "Delay Uncertainty Due to Supply Variations in Static and Dynamic Full Adders", Proc. of ISCAS 2006, pp. 767-770, Kos (Greece), May 2006.

M. Alioto, G. Palumbo, "Nanometer MCML Gates: Models and Design Considerations", Proc. of ISCAS 2006, pp. 3862-3865, Kos (Greece), May 2006.

M. Alioto, L. Pancioni, S. Rocchi, V. Vignoli, "Analysis and Design of MCML Gates with Hysteresis", Proc. of ISCAS 2006, pp. 1263-1266, Kos (Greece), May 2006.

M. Alioto, G. Palumbo, M. Poli, "Efficient Output Transition Time Modeling in CMOS Gates with Ramp/Exponential Inputs", Proc. of ISCAS 2006, pp. 5127-5130, Kos (Greece), May 2006.

T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "A Technique to Design High Entropy Chaos-Based True Random Bit Generators", Proc. of ISCAS 2006, pp. 1183-1186, Kos (Greece), May 2006.

M. Alioto, A. D. Grasso, G. Palumbo, "Design of Cascaded ECL Gates with a Power Constraint", Proc. of PRIME 2006, pp. 233-236, Otranto (Italy), June 2006.

M. Alioto, M. Poli, S. Rocchi, V. Vignoli, "Power Modeling of Precharged Address Bus and Application to Multi-bit DPA Attacks to DES Algorithm", Proc. of PATMOS 2006, pp. 593-602, Montpellier (France), Sept. 2006.

M. Alioto, M. Poli, S. Rocchi, V. Vignoli, "Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis", Proc. of PATMOS 2006, pp. 624-633, Montpellier (France), Sept. 2006.

T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "Entropy Enhancement in a Chaos-Based True Random Bit Generators", Proc. of NOLTA 2006, pp. 372-378, Bologna (Italy), Sept. 2006.

M. Alioto, R. Mita, G. Palumbo, "A Design Methodology for High-Speed Low-Power MCML Frequency Dividers", Proc. of ICECS2006, pp. 1308-1311, Nice (France), Dec. 2006.

M. Alioto, G. Palumbo, "Modeling of Delay Variability due to Supply Variations in Pass-Transistor and Static Full Adders", Proc. of ICECS2006, pp. 518-521, Nice (France), Dec. 2006.

T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "Efficient Post-Processing Module for a Chaos-based Random Bit Generator", Proc. of ICECS2006, pp. 1224-1227, Nice (France), Dec. 2006.

T. Addabbo, M. Alioto, A. Fort, M. Mugnaini, S. Rocchi, V. Vignoli, "Implementation-Efficient Maximum-Period Nonlinear Congruential Generators", Proc. of IMTC 2007, Warsaw (Poland), May 2007.

M. Alioto, M. Poli, S. Rocchi, V. Vignoli, "Mixed Techniques to Protect Precharged Busses against Differential Power Analisys Attacks", Proc. of ISCAS 2007, pp. 861-864, New Orleans (USA), May 2007.

M. Alioto, G. Palumbo, "Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects", Proc. of SCAS 2007, pp. 3255-3258, New Orleans (USA), May 2007.

M. Alioto, G. Palumbo, "High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology", Proc. of ISCAS 2007, pp. 2998-3001, New Orleans (USA), May 2007.

T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "Maximum-Period PRBGs Derived From A Piecewise Linear One-Dimensional Map", Proc. of ISCAS 2007, pp. 693-696, New Orleans (USA), May 2007.

M. Alioto, G. Palumbo, "Delay Variability Due to Supply Variations in Transmission-Gate Full Adders", Proc. of ISCAS 2007, pp. 3732-3735, New Orleans (USA), May 2007.

M. Agostinelli, M. Alioto, D. Esseni, L. Selmi, "Trading off static power and dynamic performance in CMOS digital circuits: bulk versus double gate SOI MOSFETs", Proc. of ESSDERC 2007, pp. 191-194, Munich (Germany), Sept. 2007.

M. Alioto, M. Poli, S. Rocchi, V. Vignoli, "A General Model of DPA Attacks to Precharged Busses in Symmetric-Key Cryptographic Algorithms", Proc. of ECCTD 2007, pp. 368-371, Sevilla (Spain), Aug. 2007.

M. Alioto, G. Palumbo, "Very High-Speed Carry Computation based on Mixed Dynamic/Transmission-Gate Full Adders", Proc. of ECCTD 2007, pp. 799-802, Sevilla (Spain), Aug. 2007.

M. Alioto, G. Palumbo, M. Poli, "Energy Consumption in RLC Tree Circuits", Proc. of ECCTD 2007, pp. 771-774, Sevilla (Spain), Aug. 2007.

M. Alioto, "A Simple and Accurate Model of Input capacitance for Power Estimation in CMOS logic", Proc. of ICECS 2007, pp. 431-434, Marrakech (Morocco), Dec. 2007.

M. Alioto, G. Palumbo, M. Poli, "Efficient and Accurate Models of Output Transition Time in CMOS Logic", Proc. of ICECS 2007, pp. 1264-1267, Marrakech (Morocco), Dec. 2007.

M. Alioto, M. Poli, S. Rocchi, "A General Model for Differential Power Analysis Attacks to Static Logic Circuits", in Proc. of ISCAS 2008, pp. 3346-3349, Seattle (USA), May 2008.

M. Alioto, G. Palumbo, "Power-Delay Optimization in MCML Tapered Buffers", in Proc. of ISCAS 2008, pp. 141-144, Seattle (USA), May 2008.

M. Alioto, G. Palumbo, M. Poli, "Explicit Energy Evaluation in RLC Tree Circuits with Ramp Inputs", in Proc. of ISCAS 2008, pp. 2865-2868, Seattle (USA), May 2008.

A. Tajalli, F. K. Gurkaynak, Y. Leblebici. M. Alioto, E. J. Brauer, "Improving the Power-Delay Product in SCL Circuits Using Source Follower Output Stage", in Proc. of ISCAS 2008, pp. 145-148, Seattle (USA), May 2008.

M. Alioto, L. Fondelli, S. Rocchi, "Analysis and Performance Evaluation of Area-Efficient True Random Bit Generators on FPGAs", in Proc. of ISCAS 2008, pp. 1572-1575, Seattle (USA), May 2008.

M. Alioto, G. Palumbo, M. Poli, “Energy Evaluation in RLC Tree Circuits with Exponential Input,” accepted to ICECS 2008, Malta, Aug. 2008.

M. Alioto, G. Palumbo, M. Pennisi, “Analysis of the impact of process variations on static logic circuits versus fan-in,” accepted to ICECS 2008, Malta, Aug. 2008.

M. Alioto, G. Palumbo, M. Pennisi, “Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic,” accepted to PATMOS 2008, Lisbon (Portugal), Sep. 2008.

Matteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi, “Design and evaluation of mixed 3T-4T FinFET stacks for leakage reduction,” accepted to PATMOS 2008, Lisbon (Portugal), Sep. 2008.

Armin Tajalli, Massimo Alioto, Elizabeth J. Brauer, Yusuf Leblebici, “Design of High Performance Subthreshold Source-Coupled Logic Circuits,” accepted to PATMOS 2008, Lisbon (Portugal), Sep. 2008.

M. Alioto, Y. Leblebici “Circuit techniques to reduce the supply voltage limit of subthreshold MCML circuits,” in Proc. of VLSI-SoC 2008, pp. 239-244, Rhodes Island (Greece), Oct. 2008. (INVITED)

M. Alioto, M. Poli, S. Rocchi, “Power Analysis Attacks to Cryptographic Circuits: a Comparative Analysis of DPA and CPA,” in Proc. of ICM 2008, pp. 308-311, Sharjah (United Arab Emirates), Dec. 2008.

M. Alioto, M. Poli, G. Palumbo, “Compact and Simple Output Transition Time Model in Nanometer CMOS Gates,” in Proc. of ICM 2008, pp. 235-238, Sharjah (United Arab Emirates), Dec. 2008.

M. Alioto, “CAD Models of the Input Admittance of RC Wires: Comparison and Selection Strategies,” in Proc. of ICM 2008, pp. 154-157, Sharjah (United Arab Emirates), Dec. 2008.

M. Alioto, S. Badel, Y. Leblebici, “Optimization of Wire Grid Size for Differential Routing and Impact on the Power-Delay-Area Tradeoff,” in Proc. of ISCAS 2009, pp. 1285-1288, Taipei (Taiwan), May 2009.

M. Alioto, “Understanding Loading Effects of RC Uniform Interconnects,” in Proc. of ISCAS 2009, pp. 2269-2272, Taipei (Taiwan), May 2009.

M. Alioto, Y. Leblebici, “Analysis and Design of Ultra-Low Power Subthreshold MCML Gates,” in Proc. of ISCAS 2009, pp. 2557-2560, Taipei (Taiwan), May 2009.

M. Alioto, E. Consoli, G. Palumbo, “Metrics and Design Considerations on the Energy-Delay Tradeoff of Digital Circuits,” in Proc. of ISCAS 2009, pp. 3150-3153, Taipei (Taiwan), May 2009.

M. Alioto, E. Consoli, G. Palumbo, M. Pennisi, “Correct Procedures to Evaluate the Effect of Intradie Variations on the Delay Variability of Digital Circuits,” accepted to ECCTD 2009, Antalya (Turkey), Aug. 2009.

M. Alioto, E. Consoli, G. Palumbo, “Impact of Clock Slope on Energy/Delay of Pulsed Flip-Flops and Optimum Clock Domain Design,” accepted to ECCTD 2009, Antalya (Turkey), Aug. 2009.

M. Alioto, “Analysis and Evaluation of Layout Density of FinFET Logic Gates,” accepted to ICM 2009, Marrakech (Morocco), Dec. 2009.

M. Alioto, L. Giancane, G. Scotti, A. Trifiletti, “Leakage Power Analysis Attacks: Well-Defined Procedure and First Experimental Results,” accepted to ICM 2009, Marrakech (Morocco), Dec. 2009.

M. Alioto, M. Poli, S. Rocchi, “Low-Overhead Countermeasures to protect Pre-charged Busses against Power Analysis Attacks,” accepted to ICM 2009, Marrakech (Morocco), Dec. 2009.

M. Alioto, E. Consoli, G. Palumbo, “Dependence of Differential Flip-Flops Performance on Clock Slope and Relaxation of Clock Network Design,” accepted to ICM 2009, Marrakech (Morocco), Dec. 2009.

M. Alioto, L. Giancane, G. Scotti, A. Trifiletti, “Leakage Power Analysis Attacks: Theoretical Analysis and Impact of Variations,” accepted to ICECS 2009, Hammamet (Tunisia), Dec. 2009.

M. Alioto, G. Palumbo, M. Pennisi, “Analysis of the Impact of Random Process Variations in CMOS Tapered Buffers,” accepted to ICECS 2009, Hammamet (Tunisia), Dec. 2009.

M. Alioto, E. Consoli, G. Palumbo, “Optimum Clock Slope for Flip-Flops Within a Clock Domain: Analysis and a Case Study,” accepted to ICECS 2009, Hammamet (Tunisia), Dec. 2009.

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My bookmarks:

IEEE Trans. on VLSI Systems Microelectronics Journal Integration – the VLSI Journal

IEEE Trans. on CAS – part I IEEE Trans. on CAS – part II Int. Journal of Circuit Theory and Applications

VSA-TC homepage