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Automatic Design Scaling
Omid Rowhani, M.S. 1999, advisor: Bob
Brodersen
The fast progress
towards ever smaller feature sizes renders many designs practically obsolete in a short period of time. Thus technology’s rapid pace
increases the importance and attractiveness of design
reuse, but having to re-design the circuits each time the process changes is
expensive. While the main challenge in the past was creating a chip
with a single functionality and an acceptable
performance, the emphasis is shifting towards entire systems on one chip which
will be based on reusable cores. With this trend, the challenges and
requirements of today’s designer have changed too. A
method, therefore, that will quickly and efficiently provide the designer with these blocks in the latest technology, without
sacrificing performance and requiring large amounts of
time and effort is highly desirable. The goal of this
project was to create such a methodology and to provide a tool which the designer can use to convert existing designs for use in the
latest technology. Our method is based on a program
written in Cadence’s Skill code, which performs a series of shrink and expand operations on the existing layout. These operations create
a new layout that conforms to the new target design
rules. To demonstrate the
operation of our program, and to study its advantages and short-falls, we used an ARM8 microprocessor designed in a 0.6 micron technology and
translated it to a 0.25 technology. This scaled down ARM8
will act as a core processor in the Berkeley Pleiades project
[1]. The ARM8 is a low-power 32-bit RISC microprocessor fully implemented in static
CMOS. It consists of a 5-stage pipelined Core and a branch
predicting Prefetch Unit. The Prefetch Unit together with
a double-bandwidth memory interface act to reduce the power consumption and the overall CPI. Since the memory interface’s bandwidth is
greater than the bandwidth requirement of the Core, the Prefetch Unit takes advantage of
that by buffering the instructions in a prefetch buffer.
Branch prediction is then used to remove some instructions before they are presented to the core. Thus, fewer instructions are
passed to the core for processing. Pipelining of the
instructions and the data ensure a continuous operation of the processor and the memory system.
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