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Paramererizable Multiplier Library
Hungchi Lee, M.S. 1999
Multiplication is an
important part of real-time digital signal processing (DSP) applications ranging from digital filtering to image processing. The
multipliers used in such applications require many
different operand size. An efficient way to design multipliers
with different sizes is through the design of the parameterized cells. A parameterized cell is a graphic, programmable cell that lets you
create a customized instance each time you place it by
allowing the designer to specify certain parameters. The
parameter is a setting that can control the size, shape, or contents of the cell instance.
The big advantage in using parameterized cell is that you can
speed up the time of chip design by eliminating the need
to create a lot of chips with the same function but different sizes. Also, parameterized cells can save disk space by creating a
library of cells for similar parts that are all used the
same cells.(for example in my design the regular multiplier,
complex multiplier and multiplier-accumulator are almost use the same cells).
However, parameterized design is not the only
considerations; low power dissipation and small chip area
are also needed because of the dense packing of transistors in today’s DSP
chips. The main objective of this
thesis is to design a parameterized cell library by using Cadence CAD tool, called "parameterized cell
(Pcell)", to
automatically generate a 16x16-bit multiplier, a
12x12-bit complex number multiplier and a 12x12-bit complex number
multiplier-accumulator(MAC) for the second-generation digital backend
receiver.
The three main considerations for the design
are a high multiplication speed, low power dissipation,
and a small rectangular chip area. All the designs are
using SGS-THOMPSON MICROELECTRONICS’s HCMOS7 0.25um
technology. All layout and logic testing are done with Cadence CAD tools with
Unicad design kit, and EPIC. All delay and power simulation are done
with Meta Software’s HSpice and PowerMill.
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