Reconfigurable Memory Processor for Multiprocessor DSP

John M. Thendean,  M.S. 1999  (advisor: Jan Rabaey).

As the speed of VGI processors increases, the off-chip communication delay becomes more significant. The input/output processor (I/O processor) of the VGI chip has been designed to be able to accommodate two-clock cycle off-chip communication delay. Consequently, the off-chip data access becomes more expensive. To overcome this limitation, the memory processor is designed to integrate data memory with the processing elements on the chip. The on-chip memory is therefore a cache for the processing elements, storing frequently accessed data and immediate computation results. The memory processor is intended to make memory access simpler. It follows the same data-driven handshake protocol as the VGI processing elements. Thus, the data transfer between a memory element and processing element can be done in the same way as the data transfer between processing elements. The homogeneity of the communication protocol is maintained. The memory processor also manages four memory access modes common in signal processing applications, i.e.: random access, table look-up, first-in-first-out (FIFO) and delay line. Since the address generation in FIFO and delay line modes is very simple, allocating a processing element to do the task could be a waste of the computational resources. Therefore, counters are added to the memory processor to handle FIFO and delay line address generation. This report describes the design of the VGI memory processor. The organization of the report is as follows. In chapter 2, a brief description of the VGI architecture is presented to highlight the architectural requirements of the memory processor. The rest of the chapter describes the memory processor operation and architecture. Some of the implementation issues and design decisions are discussed in Chapter 3. In Chapter 4, the simulation setup and test cases for verification are explained. Some implementations using the memory processor are included to show the communication capability between processors and memory. Finally, a summary and future works are provided in Chapter 5.